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CCD Signal Processor with Precision TimingTM Generator AD9937
FEATURES 12 MSPS Correlated Double Sampler (CDS) 10-Bit 12 MHz A/D Converter No Missing Codes Guaranteed 6 dB to 40 dB Variable Gain Amplifier (VGA) Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core with 1.7 ns Resolution On-Chip: 6-Channel Horizontal and 1-Channel RS Drivers 4-Phase Vertical Transfer Clocks Electronic and Mechanical Shutter Modes On-Chip Sync Generator with External Sync Option APPLICATIONS Digital Still Cameras Industrial Imaging GENERAL DESCRIPTION
The AD9937 is a highly integrated CCD signal processor. It includes a complete analog front end with A/D conversion, combined with a full-function programmable timing generator. A Precision Timing core allows adjustment of high speed clocks with 1.7 ns resolution at 12 MHz operation. The AD9937 is specified at pixel rates of up to 12 MHz. The analog front end includes black level clamping, CDS, VGA, and a 10-bit A/D converter. The timing generator provides all the necessary CCD clocks: RS, H-clocks, V-clocks, sensor gate pulses, and substrate charge reset pulse. Operation is programmed using a 3-wire serial interface. The AD9937 is packaged in a 56-lead LFCSP and specified over an operating temperature range of -25C to +85C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9937
6dB TO 40dB VREF 10 CDS VGA ADC DOUT
CLAMP INTERNAL CLOCKS RS 6 HORIZONTAL DRIVERS PRECISION TIMING GENERATOR
VCLK
H1 A-D H2 A, B V1 A/B V2 V3 A/B V4 TG1A TG1B TG3A TG3B
4 V-H CONTROL 4 SYNC GENERATOR
INTERNAL REGISTERS
LM
OFD
HD
VD
VCKM
SLD SCK SDA
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AD9937
TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3 ANALOG SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 5 ABSOLUTION MAXIMUM RATINGS . . . . . . . . . . . . . . . 5 PACKAGE THERMAL CHARACTERISTICS . . . . . . . . . 5 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Peak Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Total Output Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 EQUIVALENT CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . 7 TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 8 REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . 18 Control Register Serial Interface . . . . . . . . . . . . . . . . . . . 18 System and Mode Register Serial Interface . . . . . . . . . . . 18 Page/Burst Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Random Access Option . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Internal Power-On Reset Circuitry . . . . . . . . . . . . . . . . . . 19 VD Synchronous and Asynchronous Register Operation . 19 Asynchronous Register Operation . . . . . . . . . . . . . . . . . . 19 VD Synchronous Register Operation . . . . . . . . . . . . . . . . 19 SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ANALOG FRONT END DESCRIPTION AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 21 PRECISION TIMING HIGH SPEED TIMING GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 High Speed Clock Programmability . . . . . . . . . . . . . . . . . 22 H-Driver and RS Outputs . . . . . . . . . . . . . . . . . . . . . . . . 22 MASTER AND SLAVE MODE OPERATION . . . . . . . . . 25 HORIZONTAL AND VERTICAL TIMING . . . . . . . . . . . Individual HMASK Sequence . . . . . . . . . . . . . . . . . . . . . Individual PBLK Sequences . . . . . . . . . . . . . . . . . . . . . . Controlling CLPOB Clamp Pulse Timing . . . . . . . . . . . . Vertical Sensor Transfer Gate Timing . . . . . . . . . . . . . . . SHUTTER TIMING CONTROL . . . . . . . . . . . . . . . . . . . Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . . Controlling LM Pulse Timing . . . . . . . . . . . . . . . . . . . . . SPECIAL HORIZONTAL PATTERN TIMING . . . . . . . . MASKING H1 AND H2 OUTPUTS . . . . . . . . . . . . . . . . . Horizontal Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vertical Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . CCD REGIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STANDBY SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . POWER-DOWN SEQUENCE . . . . . . . . . . . . . . . . . . . . . . CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 28 29 29 29 29 31 32 33 33 33 35 35 39 40 41 42 44
TABLES Table I. Control Register Map . . . . . . . . . . . . . . . . . . . . . . . . 9 Table II. VTP Sequence System Register Map . . . . . . . . . . 10 Table III. H/LM System Register Map . . . . . . . . . . . . . . . . 12 Table IV. Shutter System Register Map . . . . . . . . . . . . . . . . 13 Table V. Mode_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table VI. Mode_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table VII. Serial Interface Registers . . . . . . . . . . . . . . . . . . 18 Table VIII. RS, H1, SHP, SHD, and DOUTPHASE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table IX. Precision Timing Edge Locations for RS, H1, SHP, SHD, and DOUTPHASE . . . . . . . . . . . . . . . . . . . . . 23 Table X. HD and VD Registers . . . . . . . . . . . . . . . . . . . . . . 25 Table XI. PBLK Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table XII. CLPOB Registers . . . . . . . . . . . . . . . . . . . . . . . . 28 Table XIII. TG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table XIV. OFD Registers . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table XV. LM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table XVI. Special H Pattern Registers . . . . . . . . . . . . . . . . 33 Table XVII. Sequence Change Positions Registers . . . . . . . 35 Table XVIII. Start-Up Polarities . . . . . . . . . . . . . . . . . . . . . 39
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AD9937-SPECIFICATIONS
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RSVDD (RS Driver) HVDD1 (H1A, H2A, and H1C Drivers) HVDD2 (H1B, H2B, and H1D Drivers) DRVDD (Data Output Drivers) DVDD (Digital) POWER CONSUMPTION @ 10 MHz Power from (AVDD + TCVDD + DRVDD + DVDD) Power from (HVDD1 + HVDD2)1 Power from (RSVDD)2 Standby Mode (AFE_STBY and DIG_STBY = 0) VCKM MAX CLOCK RATE
NOTES
H1A H2A H1B H2B H1C H1D
Min -25 -65 2.7 2.7 2.7 2.7 2.7 2.7 2.7
Typ
Max +85 +150
Unit C C V V V V V V V mW mW mW mW MHz
3.0 3.0 3.0 3.0 3.0 3.0 3.0 100 25 3 1.5
3.6 3.6 3.6 3.6 3.6 3.6 3.6
12
30
30
30
30
30
30
10pF 30pF
10pF 50pF
10pF 30pF
10pF 50pF
10pF 10pF 30pF
10pF 30pF
RS
30 10pF 10pF
1
H1 (A-D) and H2 (A, B) Loads
2
RS Load
DIGITAL SPECIFICATIONS
Parameter
(RSVDD = HVDD = 2.7 V to 3.6 V, -25 C to +85 C, unless otherwise noted.)
Symbol VIH VIL IIH IIL CIN VOH VOL VOH VOL Min 2.1 0.6 40 40 10 DRVDD - 0.5 0.5 DVDD - 0.5 0.5 12.25 12.25 100 VOH VOL RSVDD - 0.5 0.5 12.25 100 -3- Typ Max Unit V V A A pF V V V V mA mA pF V V mA pF
LOGIC INPUTS (VCKM, SLD, SDA, and SCK) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS (Except H1(A-D), H2(A, B), and RS) High Level Output Voltage @ IOH = 2 mA Low Level Output Voltage @ IOL = 2 mA H-DRIVER OUTPUTS (H1(A-D), H2(A, B)) High Level Output Voltage @ Max Current Low Level Output Voltage @ Max Current H1(A-D) Maximum Output Current (Programmable) H2(A, B) Maximum Output Current (Programmable) Maximum Load Current RS-DRIVER OUTPUTS High Level Output Voltage @ Max Current Low Level Output Voltage @ Max Current RS Maximum Output Current (Programmable) Maximum Load Current
Specifications subject to change without notice.
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AD9937 ANALOG SPECIFICATIONS
Parameter CDS Allowable CCD Reset Transient Max Input Range before Saturation Max CCD Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA) Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain (VGA Code 0) Max Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Min Clamp Level Max Clamp Level A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code 17) Max Gain (VGA Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR)
*Input signal characteristics defined as follows:
500mV TYP RESET TRANSIENT
(AVDD = 3 V, fCLI = 12 MHz, -25 C to +85 C, unless otherwise noted.)
Min Typ 500 1.0 100 2.0 10 Guaranteed 5.3 41.1 255 0 63.75 10 0.4 Guaranteed 2.0 2.0 1.0 1.0 dB dB Steps LSB measured at ADC output. LSB LSB Bits LSB V V V Includes entire signal chain. 5 40.2 6 41.2 0.1 0.3 40 7 42.2 dB dB % LSB rms dB Gain = (0.035 x Code) + 5.4 dB 12 dB gain applied. AC ground input, 6 dB gain applied. Measured with step change on supply. Max Unit mV V p-p mV V p-p Bits Notes Input signal characteristics.*
40
100mV MAX OPTICAL BLACK PIXEL
1V MAX INPUT SIGNAL RANGE
Specifications subject to change without notice.
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AD9937 TIMING SPECIFICATIONS
Parameter MASTER CLOCK, VCKM VCKM Clock Period VCKM High/Low Pulsewidth Delay from VCKM Rising Edge to Internal Pixel Position 0 AFE CLAMP PULSES CLPOB Pulsewidth2
1
(CL = 20 pF, AVDD = DVDD = DRVDD = 3 V, fCLI = 12 MHz, unless otherwise noted.)
Symbol tCONV tVCKMDLY 2 Min 83.33 41.67 9 20 41.67 9 9 10 10 10 10 10 10 Typ Max Unit ns ns ns Pixels ns ns Cycles MHz ns ns ns ns ns
AFE SAMPLE LOCATION (See Figure 13) SHP Sample Edge to SHD Sample Edge DATA OUTPUTS Output Delay from VCLK Rising Edge Pipeline Delay from SHP/SHD Sampling (See Figure 40) SERIAL INTERFACE Maximum SCK Frequency SLD to SCK Setup Time SCK to SLD Hold Time SDA Valid to SCK Rising Edge Setup SCK Falling Edge to SDA Valid Hold SCK Falling Edge to SDA Valid Read
1
tS1 tOD
33.34
fSCLK tLS tLH tDS tDH tDV
NOTES 1 Parameter is programmable. 2 Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS With Respect To Min AVSS TCVSS HVSS RSVSS DVSS DRVSS RSVSS HVSS DVSS DVSS DVSS AVSS AVSS -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
PACKAGE THERMAL CHARACTERISTICS Thermal Resistance
JA
= 24.9C/W
Parameter AVDD TCVDD HVDD RSVDD DVDD DRVDD RS Output H1(A-D), H2(A, B)Output Digital Outputs Digital Inputs SCK, SLD, SDA VRT, VRB CCDIN Junction Temperature Lead Temperature, 10 sec
Max +3.9 +3.9 +3.9 +3.9 +3.9 +3.9 RSVDD + 0.3 HVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 350
Unit V V V V V V V V V V V V V C C ORDERING GUIDE
Model AD9937KCP
Temperature Range -25C to +85C
Package Description Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP)
Package Option CP-56
AD9937KCPRL
-25C to +85C
CP-56
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9937 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD9937
PIN CONFIGURATION
V3A/B TG3A DVDD V4 TG3B OFD DVSS SCK SDA SLD
VD HD
LM
56 55 54 53 52 51 50 49 48 47 46 45 44 43
NC 1 NC 2 D0 3 D1 4 D2 5 D3 6 DRVSS 7 DRVDD 8 D4 9 D5 10 D6 11 D7 12 D8 13 D9 14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
V2
PIN 1 IDENTIFIER
42 41 40 39 38
TG1B V1A/B TG1A REFB REFT AVSS CCDIN AVDD VCKM TCVDD TCVSS NC NC NC
AD9937
TOP VIEW (Not to Scale)
37 36 35 34 33 32 31 30 29
HVDD1
H1D
H2B
H1B
H1C H2A
H1A
RSVSS RS
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS 1
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Mnemonic NC NC D0 D1 D2 D3 DRVSS DRVDD D4 D5 D6 D7 D8 D9 VCLK HVDD2 HVSS2 H1D H2B H1B HVDD1 HVSS1 H1C H2A H1A RSVSS RS RSVDD NC NC
Type2 Description NC NC DO DO DO DO P P DO DO DO DO DO DO DO P P DO DO DO P P DO DO DO P DO P NC NC No Connect No Connect Data Output Data Output Data Output Data Output Data Output Driver Ground Data Output Driver Supply Data Output Data Output Data Output Data Output Data Output Data Output Data Output Clock Horizontal Driver Supply 2 for H1D, H2B, and H1B Horizontal Driver Ground 2 CCD Horizontal Clock 4 CCD Horizontal Clock 6 CCD Horizontal Clock 2 Horizontal Driver Supply 1 for H1C, H2A, and H1A Horizontal Driver Ground 1 CCD Horizontal Clock 3 CCD Horizontal Clock 5 CCD Horizontal Clock 1 RS Driver Ground CCD Reset Gate Clock RS Driver Supply No Connect No Connect
Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
RSVDD
HVSS2
HVDD2
HVSS1
VCLK
Mnemonic NC TCVSS TCVDD VCKM AVDD CCDIN AVSS REFT REFB TG1A V1A/B TG1B V2 TG3A V3A/B TG3B V4 LM DVDD DVSS OFD HD VD SLD SDA SCK
Type2 Description NC P P DI3 P AI P AO AO DO DO DO DO DO DO DO DO DO P P DO DO DO DI3 DI3 DI3 No Connect Analog Ground for Timing Core Analog Supply for Timing Core Reference Clock Input Analog Supply for AFE CCD Input Signal Analog Ground for AFE Voltage Reference Top Bypass Voltage Reference Bottom Bypass CCD Sensor Gate Pulse 1 CCD Vertical Transfer Clock 1 CCD Sensor Gate Pulse 2 CCD Vertical Transfer Clock 2 CCD Sensor Gate Pulse 3 CCD Vertical Transfer Clock 3 CCD Sensor Gate Pulse 4 CCD Vertical Transfer Clock 4 Line Memory Control Pulse Digital Supply Digital Ground CCD Substrate Reset Pulse Horizontal Sync Pulse Vertical Sync Pulse 3-Wire Serial Load Pulse 3-Wire Serial Data 3-Wire Serial Clock
NOTES 1 See Figure 41 for circuit configuration. 2 AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input/Output, P = Power, NC = No Connection. 3 Schmitt trigger type input.
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AD9937
TERMINOLOGY Differential Nonlinearity (DNL) Total Output Noise
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes must be present over all operating conditions.
Peak Nonlinearity
The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship
1 LSB = ADC Full Scale 2N codes
(
)
Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9937 from a true straight line. The point used as zero scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC fullscale signal. The input signal is always appropriately gained up to fill the ADC's full-scale range.
where N is the bit resolution of the ADC. For the AD9937, 1 LSB is 1.95 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply pins. This represents a very high frequency disturbance on the AD9937's power supply. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.
EQUIVALENT CIRCUITS
DVDD
AVDD
330
R
AVSS
AVSS
DVSS
Figure 1. CCDIN
Figure 3. Digital Inputs
HVDD1, HVDD2, OR RSVDD RS, H1 (A-D), H2 (A, B)
DVDD DATA
DRVDD
TRISTATEOUT
DOUT
ENABLE
OUTPUT
DVSS
DRVSS
HVSS1, HVSS2, OR RSVSS
Figure 2. Digital Data Outputs
Figure 4. H1(A-D), H2(A, B), and RS Drivers
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AD9937-Typical Performance Characteristics
160
0.50
150
POWER DISSIPATION - mW
VDD = 3.3V 140
0.25
DNL - LSB
130
VDD = 3.0V
0
VDD = 3.0V
120 VDD = 2.7V 110
-0.25
100 8 10 SAMPLE RATE - MHz 12
-0.50 0 200 400 CODE 600 800 1000
TPC 1. Power vs. Sample Rate
TPC 2. Typical DNL Performance
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AD9937
Table I. Control Register Map
Addr 0 1
Bit Bit Breakdown Width (23:0) 0 (23:1) 24 1 23 2 1 21 8 1 1 1 1 1 1 1 2 1 1 5 1 1 1 1 1 1 18 6 6 6 2 1 1 1 1 6 6 6 6 3 3 3 15 23
Default 0 0
Register Name SW_RESET OUTCONT_REG Unused
Function Software Reset = 000000 (Reset All Registers to Default). Internal OUTCONT Signal Control (0 = Digital Outputs held at fixed dc level, 1 = Normal Operation). AFE Standby (0 = Full Standby, 1 = Normal Operation, 2/3 = Reference Standby). Digital Standby (0 = Full Standby, 1 = Normal Operation). Black Clamp Level. 1 = Black Clamp Enable. This register should always be set to 0. This register should always be set to 0. 0 = Blank to 0, 1 = Blank to Clamp Level (REFBLACK). 0 = Data Outputs are Driven, 1 = Data Outputs are Three-Stated. 0 = Retime Data Outputs, 1 = Do Not Retime Data Outputs. 1 = Gray Encode ADC Outputs. This register should always be set to 0. This register should always be set to 0. This register should always be set to 1. VCKM Input Clock Divider (0 = VCKM, 1 = VCKM/2). Retimes the H1 HBLK to Internal Clock. LM Inversion Control (1 = Invert Programmed LM). TG and OFD Inversion Control (1 = Invert Programmed TG and ODF). VD and HD Inversion Control (1 = Invert Programmed VD and HD; Note that Internal VD/HD Are HI Active). Operating Mode (0 = Slave Mode, 1 = Master Mode). SHD Sample Location. SHP Sample Location. Data Output [9:0] and VCLK Phase Adjustment. Data Output Clock Selection (0 = No Delay, 1 = ~4 ns, 2 = ~8 ns, 3 = ~12 ns). VCLK Masking Control (1 = Mask). 1 = Invert VCLK. 1 = Internal Digital Signal Test Mode. H1 Positive Edge Location. H1 Negative Edge Location. RS Positive Edge Location. RS Negative Edge Location. H1A/B/C/D Drive Strength (0 = OFF, 1 = 1.75 mA, 2 = 3.5 mA, 3 = 5.25 mA, 4 = 7 mA, 5 = 8.75 mA, 6 = 10.5 mA, 7 = 12.25 mA). H2A/B Drive Strength (see H1DRV). RS Drive Strength (see H1DRV).
2
(1:0) 2 (23:3)
0 0 0x80 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0x00 0x24 0x00 0x00 0 1 0 - 0x00 0x20 0x00 0x10 4 4 4
AFE_STBY DIG_STBY Unused REFBLACK BC_EN TESTMODE TESTMODE PBLK_LEVEL TRISTATEOUT RETIMEOUT_BAR GRAY_ENCODE TESTMODE TESTMODE TESTMODE Unused VCKM_DIVIDE H1BLKRETIME LM_INVERT TGOFD_INVERT VDHD_INVERT MASTER Unused SHDLOC SHPLOC DOUTPHASE DOUT_DELAY VCLKMASK VCLK_INVERT DTEST Unused H1POSLOC H1NEGLOC RSPOSLOC RSNEGLOC H1DRV H2DRV RSDRV Unused Unused
3
(7:0) 8 9 10 11 12 13 14 (16:15) 17 18 (23:19) 0 1 2 3 4 5 (23:6)
4
5
(5:0) (11:6) (17:12) (19:18) 20 21 22 23
6
(5:0) (11:6) (17:12) (23:18) (2:0) (5:3) (8:6) (23:9) (23:1)
7
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AD9937
Table I. Control Register Map (continued)
Addr 8 9
Bit Bit Breakdown Width 0 (23:1) 0 (4:1) (23:5) 0 (11:1) 12 (23:13) (11:0) (23:12) (9:0) (23:10) 1 23 1 4 19 1 11 1 11 12 12 10 14
Default 0 1 0x9 1 0x7FF 1 4095 4095 0x000
Register Name MODE Unused SPEN SPLOGIC Unused OFDEN OFDNUM TGEN Unused OFDHPTOG1 OFDHPTOG2 VGAGAIN Unused
Function Mode Control Bit. (0 = Mode A, 1 = Mode B) Single Pulse (SP) Output Enable. Single Pulse Logic Setting (0 = OR, 1 = AND). OFD Output Enable Control (0 = Disable, 1 = Enable). Total Number of OFD Pulses per Field. TG Output Enable Control (0 = Disable, 1 = Enable). High Precision OFD Toggle Position 1. High Precision OFD Toggle Position 2. VGA Gain Control.
10
11 12
Denotes VD synchronous registers (control addresses 8, 9, 10, 11, and 12).
Table II. VTP Sequence System Register Map (Addr 0x14)
Addr VTP_Reg(0)
Bit Breakdown (11:0) (23:12) (31:24) (8:0) (17:9) (26:18) 27 28 29 30 31 (8:0) (17:9) (26:18) (31:27) (8:0) (17:9) (26:18) (31:27) (8:0) (17:9) (26:18) 27 28 29 30 31 (8:0) (17:9) (26:18) (31:27)
Bit Width 12 12 8 9 9 9 1 1 1 1 1 9 9 9 5 9 9 9 5 9 9 9 1 1 1 1 1 9 9 9 5
Default
Register Name ENDADDRESS STARTADDRESS VTP_Reg_Addr
Function Sub Word End Address Sub Word Start Address System Register Address 0x14 VTP0: Length between Repetitions VTP0: V1 Toggle Position 1 VTP0: V1 Toggle Position 2 VTP0: V1 Start Polarity VTP0: V2 Start Polarity VTP0: V3 Start Polarity VTP0: V4 Start Polarity VTP0: V2 Toggle Position 1 VTP0: V2 Toggle Position 2 VTP0: V3 Toggle Position 1 VTP0: V3 Toggle Position 2 VTP0: V4 Toggle Position 1 VTP0: V4 Toggle Position 2 VTP1: Length between Repetitions VTP1: V1 Toggle Position 1 VTP1: V1 Toggle Position 2 VTP1: V1 Start Polarity VTP1: V2 Start Polarity VTP1: V3 Start Polarity VTP1: V4 Start Polarity VTP1: V2 Toggle Position 1 VTP1: V2 Toggle Position 2 VTP1: V3 Toggle Position 1
VTP_Reg(1)
279 75 250 1 0 0 1 40 145 110 215 5 180 99 29 99 1 0 0 1 15 57 43
VTPLEN_0 V1TOG1_0 V1TOG2_0 V1POL_0 V2POL_0 V3POL_0 V4POL_0 Unused V2TOG1_0 V2TOG2_0 V3TOG1_0 Unused V3TOG2_0 V4TOG1_0 V4TOG2_0 Unused VTPLEN_1 V1TOG1_1 V1TOG2_1 V1POL_1 V2POL_1 V3POL_1 V4POL_1 Unused V2TOG1_1 V2TOG2_1 V3TOG1_1 Unused
VTP_Reg(2)
VTP_Reg(3)
VTP_Reg(4)
VTP_Reg(5)
-10-
REV. 0
AD9937
Table II. VTP Sequence System Register Map (Addr 0x14) (continued)
Addr VTP_Reg(6)
Bit Breakdown (8:0) (17:9) (26:18) (31:27) (8:0) (17:9) (26:18) 27 28 29 30 31 (8:0) (17:9) (26:18) (31:27) (8:0) (17:9) (26:18) (31:27) (11:0) (23:12) (31:24) (11:0) (23:12) (31:24) (11:0) (23:12) (31:24) (11:0) (23:12) (31:24)
Bit Width 9 9 9 5 9 9 9 1 1 1 1 1 9 9 9 5 9 9 9 5 12 12 8 12 12 8 12 12 8 12 12 8
Default 85 1 71 99 29 99 1 0 0 1 15 57 43 85 1 71 40 410 490 780 80 360 450 820
Register Name V3TOG2_1 V4TOG1_1 V4TOG2_1 Unused VTPLEN_2 V1TOG1_2 V1TOG2_2 V1POL_2 V2POL_2 V3POL_2 V4POL_2 Unused V2TOG1_2 V2TOG2_2 V3TOG1_2 Unused V3TOG2_2 V4TOG1_2 V4TOG2_2 Unused SP1TOG1 SP1TOG2 Unused SP2TOG1 SP2TOG2 Unused SP3TOG1 SP3TOG2 Unused SP4TOG1 SP4TOG2 Unused
Function VTP1: V3 Toggle Position 2 VTP1: V4 Toggle Position 1 VTP1: V4 Toggle Position 2 VTP2: Length between Repetitions VTP2: V1 Toggle Position 1 VTP2: V1 Toggle Position 2 VTP2: V1 Start Polarity VTP2: V2 Start Polarity VTP2: V3 Start Polarity VTP2: V4 Start Polarity VTP2: V2 Toggle Position 1 VTP2: V2 Toggle Position 2 VTP2: V3 Toggle Position 1 VTP2: V3 Toggle Position 2 VTP2: V4 Toggle Position 1 VTP2: V4 Toggle Position 2 SP1 Toggle Position 1 (V1A/V1B) SP1 Toggle Position 2 (V1A/V1B) SP2 Toggle Position 1 (V2) SP2 Toggle Position 2 (V2) SP3 Toggle Position 1 (V3A/V3B) SP3 Toggle Position 2 (V3A/V3B) SP4 Toggle Position 1 (V4) SP4 Toggle Position 2 (V4)
VTP_Reg(7)
VTP_Reg(8)
VTP_Reg(9)
VTP_Reg(10)
VTP_Reg(11)
VTP_Reg(12)
VTP_Reg(13)
REV. 0
-11-
AD9937
Table III. H/LM System Register Map (Addr 0x15)
Addr HLM_Reg(0)
Bit Breakdown (11:0) (23:12) (31:24) 0 1 2 3 4 5 (31:6) (5:0) (11:6) (17:12) (31:18) (5:0) (11:6) (17:12) (31:18) (5:0) (11:6) (17:12) (31:18) (5:0) (11:6) (17:12) (31:18) (5:0) (11:6) (17:12) (31:18) (5:0) (11:6) (17:12) (31:18) (7:0) (15:8) (23:16) (31:24) (7:0) (15:8) (23:16) (31:24)
Bit Width 12 12 8 1 1 1 1 1 1 26 6 6 6 14 6 6 6 14 6 6 6 14 6 6 6 14 6 6 6 14 6 6 6 14 8 8 8 8 8 8 8 8
Default
Register Name
Function
ENDADDRESS Sub Word End Address STARTADDRESS Sub Word Start Address HLM_Reg_Addr System Register Address 0x15 0 0 1 1 0 0 0x00 0x04 0x01 0x07 0x08 0x22 0x34 0x34 0x04 0x04 0x3A 0x0B 0x3D 0x3F 0x3C 0x3C 0x03 0x02 99 5 55 87 29 2 26 0 H1APOL H1BPOL H1CPOL H1DPOL H2APOL H2BPOL Unused SPH1A1 SPH1B1 SPH1C1 Unused SPH1D1 SPH2A1 SPH2B1 Unused SPH1A2 SPH1B2 SPH1C2 Unused SPH1D2 SPH2A2 SPH2B2 Unused SPH1A3 SPH1B3 SPH1C3 Unused SPH1D3 SPH2A2 SPH2B3 Unused LMLEN0 LMTOG1_0 LMTOG2_0 SPHSTART0 LMLEN1 LMTOG1_1 LMTOG2_1 SPHSTART1 H1A Special H-Pattern Start Polarity H1B Special H-Pattern Start Polarity H1C Special H-Pattern Start Polarity H1D Special H-Pattern Start Polarity H2A Special H-Pattern Start Polarity H2B Special H-Pattern Start Polarity H1A Special H-Pattern during LM Repetition 1 H1B Special H-Pattern during LM Repetition 1 H1C Special H-Pattern during LM Repetition 1 H1D Special H-Pattern during LM Repetition 1 H2A Special H-Pattern during LM Repetition 1 H2B Special H-Pattern during LM Repetition 1 H1A Special H-Pattern during LM Repetition 2 H1B Special H-Pattern during LM Repetition 2 H1C Special H-Pattern during LM Repetition 2 H1D Special H-Pattern during LM Repetition 2 H2A Special H-Pattern during LM Repetition 2 H2B Special H-Pattern during LM Repetition 2 H1A Special H-Pattern during LM Repetition 3 H1B Special H-Pattern during LM Repetition 3 H1C Special H-Pattern during LM Repetition 3 H1D Special H-Pattern during LM Repetition 3 H2A Special H-Pattern during LM Repetition 3 H2B Special H-Pattern during LM Repetition 3 LM Pattern 0 (LM0): LM Counter Length LM Pattern 0 (LM0): Toggle Position 1 LM Pattern 0 (LM0): Toggle Position 2 LM Pattern 0 (LM0): Special H Pulse Start Position LM Pattern 1 (LM1): LM Counter Length LM Pattern 1 (LM1): Toggle Position 1 LM Pattern 1 (LM1): Toggle Position 2 LM Pattern 1 (LM1): Special H Pulse Start Position
HLM_Reg(1)
HLM_Reg(2)
HLM_Reg(3)
HLM_Reg(4)
HLM_Reg(5)
HLM_Reg(6)
HLM_Reg(7)
HLM_Reg(8)
HLM_Reg(9)
-12-
REV. 0
AD9937
Table IV. Shutter System Register Map (Addr 0x16)
Addr Shut_Reg(0)
Bit Breakdown (11:0) (23:12) (31:24) (11:0) (23:12) (31:24) (11:0) (23:12) (31:24) (11:0) (23:12) (31:24) (11:0) (23:12) (31:24)
Bit Width 12 12 8 12 12 8 12 12 8 12 12 8 12 12 8
Default
Register Name
Function
ENDADDRESS Sub Word End Address STARTADDRESS Sub Word Start Address SHUT_Reg_Addr System Register Address 0x16 80 370 490 780 540 720 830 860 TGTOG1_0 TGTOG2_0 Unused TGTOG1_1 TGTOG2_1 Unused OFDTOG1_0 OFDTOG2_0 Unused OFDTOG1_1 OFDTOG2_1 Unused TG0 Pulse Toggle Position 1 TG0 Pulse Toggle Position 2 TG1 Pulse Toggle Position 1 TG1 Pulse Toggle Position 2 OFD0 Pulse Toggle Position 1 OFD0 Pulse Toggle Position 2 OFD1 Pulse Toggle Position 1 OFD1 Pulse Toggle Position 2
Shut_Reg(1)
Shut_Reg(2)
Shut_Reg(3)
Shut_Reg(4)
REV. 0
-13-
AD9937
Table V. Mode_A (Addr 0x17)
Addr Mode_Reg(0)
Bit Breakdown (11:0) (23:12) (31:24) (6:0) 7 8 (12:9) 13 (31:14) (11:0) (23:12) (31:24) (11:0) (23:12) (31:24) (11:0) (22:12) (26:23) (30:27) 31 (11:0) (23:12) (31:24) (11:0) (23:12) (31:24) (11:0) (23:12) 24 (31:25) (11:0) (23:12) 24 (31:25) (11:0) (23:12) (31:24)
Bit Width 12 12 8 7 1 1 4 1 18 12 12 8 12 12 8 12 11 4 4 1 12 12 8 12 12 8 12 12 1 7 12 12 1 7 12 12 8 12 12 8 11 11 10 11 11 1 9 12 12 8
Default
Register Name ENDADDRESS STARTADDRESS MODE_Reg_Addr
Function Sub Word End Address Sub Word Start Address Mode Register Address (Mode A = Addr 0x17) TG Active Line TG1A/B Pattern Selector (0 = TG0, 1 = TG1) TG3A/B Pattern Selector (0 = TG0, 1 = TG1) TG Masking Control (1 = Mask) OFD Pattern Selection (0 = OFD0, 1 = OFD1) HD Toggle Position 1 HD Toggle Position 2 HD Toggle Position 3 HD Toggle Position 4 HD Last Line Length VD Field Length VD Toggle Position 1 VD Toggle Position 2 CLPOB Toggle Position 1 CLPOB Toggle Position 2 CLPOB Toggle Position 3 CLPOB Toggle Position 4 HBLK Toggle Position 1 HBLK Toggle Position 2 H1 Polarity between Toggle Positions 1 and 2 HBLK Toggle Position 3 HBLK Toggle Position 4 H1 Polarity between Toggle Positions 3 and 4 PBLK Toggle Position 1 PBLK Toggle Position 2 PBLK Toggle Position 3 PBLK Toggle Position 4 PBLK Start Position PBLK Stop Position Vertical H Masking Start Position Vertical H Masking Stop Position Masking Polarity for H1 during Vertical Blanking Period LM Counter Start Position 1 LM Counter Start Position 2
Mode_Reg(1)
0 0 1 0xA 0 831 866 4095 4095 2339 262 0 4 1543 1557 4095 4095 0 869 0 4095 4095 0 6 878 4095 4095 255 3 0 1 0 550 4095
TGACTLINE TGPATSEL0 TGPATSEL1 TGMASK OFDPATSEL Unused HDTOG1 HDTOG2 Unused HDTOG3 HDTOG4 Unused HDLASTLEN VDLEN VDTOG1 VDTOG2 Unused CLPOBTOG1 CLPOBTOG2 Unused CLPOBTOG3 CLPOBTOG4 Unused HBLKTOG1 HBLKTOG2 H1TOG12POL Unused HBLKTOG3 HBLKTOG4 H1TOG34POL Unused PBLKTOG1 PBLKTOG2 Unused PBLKTOG3 PBLKTOG4 Unused PBLKSTART PBLKSTOP Unused HMASKSTART HMASKSTOP H1MASKPOL Unused LMSTART0 LMSTART1 Unused
Mode_Reg(2)
Mode_Reg(3)
Mode_Reg(4)
Mode_Reg(5)
Mode_Reg(6)
Mode_Reg(7)
Mode_Reg(8)
Mode_Reg(9)
Mode_Reg(10) (11:0) (23:12) (31:24) Mode_Reg(11) (10:0) (21:11) (31:22) Mode_Reg(12) (10:0) (21:11) 22 (31:23) Mode_Reg(13) (11:0) (23:12) (31:24)
-14-
REV. 0
AD9937
Table V. Mode_A (Addr 0x17) (continued)
Addr
Bit Breakdown
Bit Width 8 8 8 8 12 2 3 1 2 1 1 10 12 2 3 1 2 1 1 10 12 2 3 1 2 1 1 10 12 2 3 1 2 1 1 10 12 2 3 1 2 1 1 10
Default 1 0 0 0 1559 0 0 0 0 0 1 1559 0 2 0 3 1 1 1559 0 2 0 3 1 1 1559 0 2 0 3 1 1 1559 0 2 0 3 1 1
Register Name SCP1 SCP2 SCP3 SCP4 HDLEN0 VTPPATSEL0 VTPREP0 LMPATSEL0 LMREP0 SPHEN0 CLPOBEN0 Unused HDLEN1 VTPPATSEL1 VTPREP1 LMPATSEL1 LMREP1 SPHEN1 CLPOBEN1 Unused HDLEN2 VTPPATSEL2 VTPREP2 LMPATSEL2 LMREP2 SPHEN2 CLPOBEN2 Unused HDLEN3 VTPPATSEL3 VTPREP3 LMPATSEL3 LMREP3 SPHEN3 CLPOBEN3 Unused HDLEN4 VTPPATSEL4 VTPREP4 LMPATSEL4 LMREP4 SPHEN4 CLPOBEN4 Unused
Function Sequence Change Position 1 Sequence Change Position 2 Sequence Change Position 3 Sequence Change Position 4 HD Counter Length Value for Region 0 VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2) VTP Pulse Repetition Number in Region 0 LM Pattern Select for Region 0 (0 = LM0, 1 = LM1) LM Repetition Number in Region 0 Special H-Pattern Enable in Region 0 CLPOB Enable in Region 0 HD Counter Length Value for Region 1 VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2) VTP Pulse Repetition Number in Region 1 LM Pattern Select for Region 1 (0 = LM0, 1 = LM1) LM Repetition Number in Region 1 Special H-Pattern Enable in Region 1 CLPOB Enable in Region 1 HD Counter Length Value for Region 2 VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2) VTP Pulse Repetition Number in Region 2 LM Pattern Select for Region 2 (0 = LM0, 1 = LM1) LM Repetition Number in Region 2 Special H-Pattern Enable in Region 2 CLPOB Enable in Region 2 HD Counter Length Value for Region 3 VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2) VTP Pulse Repetition Number in Region 3 LM Pattern Select for Region 3 (0 = LM0, 1 = LM1) LM Repetition Number in Region 3 Special H-Pattern Enable in Region 3 CLPOB Enable in Region 3 HD Counter Length Value for Region 4 VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2) VTP Pulse Repetition Number in Region 4 LM Pattern Select for Region 4 (0 = LM0, 1 = LM1) LM Repetition Number in Region 4 Special H-Pattern Enable in Region 4 CLPOB Enable in Region 4
Mode_Reg(14) (7:0) (15:8) (23:16) (31:24) Mode_Reg(15) (11:0) (13:12) (16:14) 17 (19:18) 20 21 (31:22) Mode_Reg(16) (11:0) (13:12) (16:14) 17 (19:18) 20 21 (31:22) Mode_Reg(17) (11:0) (13:12) (16:14) 17 (19:18) 20 21 (31:22) Mode_Reg(18) (11:0) (13:12) (16:14) 17 (19:18) 20 21 (31:22) Mode_Reg(19) (11:0) (13:12) (16:14) 17 (19:18) 20 21 (31:22)
REV. 0
-15-
AD9937
Table VI. Mode_B (Addr 0x18)
Addr Mode_Reg(0)
Bit Breakdown (11:0) (23:12) (31:24) (6:0) 7 8 (12:9) 13 (31:14) (11:0) (23:12) (31:24) (11:0) (23:12) (31:24) (11:0) (22:12) (26:23) (30:27) 31 (11:0) (23:12) (31:24) (11:0) (23:12) (31:24) (11:0) (23:12) 24 (31:25) (11:0) (23:12) 24 (31:25) (11:0) (23:12) (31:24)
Bit Width 12 12 8 7 1 1 4 1 18 12 12 8 12 12 8 12 11 4 4 1 12 12 8 12 12 8 12 12 1 7 12 12 1 7 12 12 8 12 12 8 11 11 10 11 11 1 9 12 12 8
Default
Register Name ENDADDRESS STARTADDRESS MODE_Reg_Addr
Function Sub Word End Address Sub Word Start Address Mode Register Address (Mode B = Addr 0x18) TG Active Line TG1A/B Pattern Selector (0 = TG0, 1 = TG1) TG3A/B Pattern Selector (0 = TG0, 1 = TG1) TG Masking Control (1 = Mask) OFD Pattern Selection (0 = OFD0, 1 = OFD1) HD Toggle Position 1 HD Toggle Position 2 HD Toggle Position 3 HD Toggle Position 4 HD Last Line Length VD Field Length VD Toggle Position 1 VD Toggle Position 2 CLPOB Toggle Position 1 CLPOB Toggle Position 2 CLPOB Toggle Position 3 CLPOB Toggle Position 4 HBLK Toggle Position 1 HBLK Toggle Position 2 H1 Polarity between Toggle Positions 1 and 2 HBLK Toggle Position 3 HBLK Toggle Position 4 H1 Polarity between Toggle Positions 3 and 4 PBLK Toggle Position 1 PBLK Toggle Position 2 PBLK Toggle Position 3 PBLK Toggle Position 4 PBLK Start Position PBLK Stop Position Vertical H Masking Start Position Vertical H Masking Stop Position Masking Polarity for H1 during Vertical Blanking Period LM Counter Start Position 1 LM Counter Start Position 2
Mode_Reg(1)
0 0 1 0x0 1 95 130 830 865 1559 525 0 4 808 822 1543 1557 1 133 1 825 868 0 6 143 831 878 510 6 0 1 0 99 830
TGACTLINE TGPATSEL0 TGPATSEL1 TGMASK OFDPATSEL Unused HDTOG1 HDTOG2 Unused HDTOG3 HDTOG4 Unused HDLASTLEN VDLEN VDTOG1 VDTOG2 Unused CLPOBTOG1 CLPOBTOG2 Unused CLPOBTOG3 CLPOBTOG4 Unused HBLKTOG1 HBLKTOG2 H1TOG12POL Unused HBLKTOG3 HBLKTOG4 H1TOG34POL Unused PBLKTOG1 PBLKTOG2 Unused PBLKTOG3 PBLKTOG4 Unused PBLKSTART PBLKSTOP Unused HMASKSTART HMASKSTOP H1MASKPOL Unused LMSTART0 LMSTART1 Unused
Mode_Reg(2)
Mode_Reg(3)
Mode_Reg(4)
Mode_Reg(5)
Mode_Reg(6)
Mode_Reg(7)
Mode_Reg(8)
Mode_Reg(9)
Mode_Reg(10) (11:0) (23:12) (31:24) Mode_Reg(11) (10:0) (21:11) (31:22) Mode_Reg(12) (10:0) (21:11) 22 (31:23) Mode_Reg(13) (11:0) (23:12) (31:24)
-16-
REV. 0
AD9937
Table VI. Mode_B (Addr 0x18) (continued)
Addr
Bit Breakdown
Bit Width 8 8 8 8 12 2 3 1 2 1 1 10 12 2 3 1 2 1 1 10 12 2 3 1 2 1 1 10 12 2 3 1 2 1 1 10 12 2 3 1 2 1 1 10
Default 1 0 0 0 1559 0 0 0 0 0 1 1559 1 1 1 1 0 1 1559 1 1 1 1 0 1 1559 1 1 1 1 0 1 1559 1 1 1 1 0 1
Register Name SCP1 SCP2 SCP3 SCP4 HDLEN0 VTPPATSEL0 VTPREP0 LMPATSEL0 LMREP0 SPHEN0 CLPOBEN0 Unused HDLEN1 VTPPATSEL1 VTPREP1 LMPATSEL1 LMREP1 SPHEN1 CLPOBEN1 Unused HDLEN2 VTPPATSEL2 VTPREP2 LMPATSEL2 LMREP2 SPHEN2 CLPOBEN2 Unused HDLEN3 VTPPATSEL3 VTPREP3 LMPATSEL3 LMREP3 SPHEN3 CLPOBEN3 Unused HDLEN4 VTPPATSEL4 VTPREP4 LMPATSEL4 LMREP4 SPHEN4 CLPOBEN4 Unused
Function Sequence Change Position 1 Sequence Change Position 2 Sequence Change Position 3 Sequence Change Position 4 HD Counter Length Value for Region 0 VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2) VTP Pulse Repetition Number in Region 0 LM Pattern Select for Region 0 (0 = LM0, 1 = LM1) LM Repetition Number in Region 0 Special H-Pattern Enable in Region 0 CLPOB Enable in Region 0 HD Counter Length Value for Region 1 VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2) VTP Pulse Repetition Number in Region 1 LM Pattern Select for Region 1 (0 = LM0, 1 = LM1) LM Repetition Number in Region 1 Special H-Pattern Enable in Region 1 CLPOB Enable in Region 1 HD Counter Length Value for Region 2 VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2) VTP Pulse Repetition Number in Region 2 LM Pattern Select for Region 2 (0 = LM0, 1 = LM1) LM Repetition Number in Region 2 Special H-Pattern Enable in Region 2 CLPOB Enable in Region 2 HD Counter Length Value for Region 3 VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2) VTP Pulse Repetition Number in Region 3 LM Pattern Select for Region 3 (0 = LM0, 1 = LM1) LM Repetition Number in Region 3 Special H-Pattern Enable in Region 3 CLPOB Enable in Region 3 HD Counter Length Value for Region 4 VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2) VTP Pulse Repetition Number in Region 4 LM Pattern Select for Region 4 (0 = LM0, 1 = LM1) LM Repetition Number in Region 4 Special H-Pattern Enable in Region 4 CLPOB Enable in Region 4
Mode_Reg(14) (7:0) (15:8) (23:16) (31:24) Mode_Reg(15) (11:0) (13:12) (16:14) 17 (19:18) 20 21 (31:22) Mode_Reg(16) (11:0) (13:12) (16:14) 17 (19:18) 20 21 (31:22) Mode_Reg(17) (11:0) (13:12) (16:14) 17 (19:18) 20 21 (31:22) Mode_Reg(18) (11:0) (13:12) (16:14) 17 (19:18) 20 21 (31:22) Mode_Reg(19) (11:0) (13:12) (16:14) 17 (19:18) 20 21 (31:22)
REV. 0
-17-
AD9937
SERIAL INTERFACE TIMING System and Mode Register Serial Interface
All of the internal registers of the AD9937 are accessed through a 3-wire serial interface. The 3-wire interface consists of a clock (SCK), serial load (SLD), and serial data (SDA). The AD9937 has three different register types that are configured by the 3-wire serial interface pins. As described in Table VII, the three register types are control registers, system registers, and mode registers.
Table VII. Serial Interface Registers
The AD9937 provides two options for writing to system and mode registers. The Page/Burst write option is used when all the registers are going to be written to, whereas the Random Access option is used when only one or a small contiguous sequence of registers is going to be written to. As shown in Figure 6, the protocol for writing to system and mode registers requires eight bits for the address data, 12 bits for the start location, 12 bits for the end location, and 32 bits for the register data.
Page/Burst Option
Register Control Registers VTP Sequence System Registers H/LM System Registers Shutter System Registers Mode_A
Address 0x00 to 0x12 0x14
No. of Registers 24-Bit Register at Each Address. See Table I. Fourteen 32-Bit System Registers at Address 0x14. See Table II. Ten 32-Bit System Registers at Address 0x15. See Table III. Five 32-Bit System Registers at Address 0x16. See Table IV. Twenty 32-Bit Mode_A Registers at Address 0x17. See Table V. Twenty 32-Bit Mode_B Registers at Address 0x18. See Table VI.
The AD9937 is automatically configured for Page/Burst mode if both 12-bit STARTADDRESS and ENDADDRESS fields equal 0. In this configuration, the AD9937 expects all registers to be written to, therefore all register data must be clocked in before the SLD pulse is asserted high. The SLD pulse is ignored until all register data is clocked in. The Page/Burst option is preferred when initially programming the system and mode registers at startup.
Random Access Option
0x15
0x16
0x17
With the Random Access option, the 12-bit STARTADDRESS and ENDADDRESS fields are typically used when writing to one system or mode register or a small sequential number of system or mode registers. In this mode, the address data selects the system or mode register bank that is going to be accessed, the 12-bit STARTADDRESS determines the first register to be accessed, and the 12-bit ENDADDRESS determines the last register to be accessed. Two examples of Random Access are provided below (refer to Figure 6).
Example 1: Accessing Only One Register, HLM_Reg(6)
Mode_B
0x18
Control Register Serial Interface
HLM_Reg_addr[A7:A0] = 0x15 STARTADDRESS[S11:S0] = 0x0006 ENDADDRESS[E11:E0] = 0x0006
Example 2: Accessing HLM_Reg(2), HLM_Reg(3), and HLM_Reg(4) Sequentially
The control register 3-wire interface timing requirements are shown in Figure 5. Writing to control registers requires eight bits of address data followed by 24 bits of configuration data between each active low period of SLD for each address. The SLD signal must be kept high for at least one full SCK cycle between successive writes to control registers.
HLM_Reg_addr[A7:A0] = 0x15 STARTADDRESS[S11:S0] = 0x0002 ENDADDRESS[E11:E0] = 0x0004
SDA
A7
A6
A5
A4
A3
A2
A1
A0
D23
D22
D21
....
D3
D2
D1
D0
t DS
SCK 1
t DH
.... 2 3 4 5 6 7 8 9 10 11 29 30 31 32
t LS
SLD 1. SDA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. THIS TIMING PATTERN MUST BE WRITTEN FOR EACH REGISTER WRITE WITH SLD REMAINING HIGH FOR AT LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SLD LOW AGAIN FOR THE NEXT REGISTER WRITE.
t LH
Figure 5. 3-Wire Serial Interface Timing for Control Registers
-18-
REV. 0
AD9937
8-BIT REG ADDRESS [7:0] 12-BIT START ADDRESS [11:0] 12-BIT END ADDRESS[11:0] 32-BIT DATA 0 [31:0] 32-BIT DATA N [31:0]
D31 D30 D29
E2 E1 E0 D31
S1 S0 E11 E10
D30 D29
S11 S10
A7 A6 A5
A4 A3 A2
A1 A0
S3
S9
S8
S2
E9
E3
D3
D3
8 BIT ADDRESS
START LOCATION ADDRESS
END LOCATION ADDRESS
DATA 0 [31:0]
D2 D1 D0
SDA
DATA N [31:0]
SCK
SLD
1
1
1
1. ALL SLD PULSES ARE IGNORED UNTIL THE LAST BIT OF THE LAST DATA N WORD IS CLOCKED IN. 2. THE SLD PULSE MUST BE ASSERTED HIGH WHEN ALL SDA DATA TRANSMISSIONS HAVE BEEN COMPLETED.
Figure 6. System and Mode Register Writes
Internal Power-On Reset Circuitry
Asynchronous Register Operation
After power-on, the AD9937 automatically resets all internal registers and performs internal calibration procedures. This takes approximately 1 ms to complete. During this time, normal clock signals and serial write operations may occur. However, serial register writes are ignored until the internal reset operation is completed.
VD Synchronous and Asynchronous Register Operation
For asynchronous register writes, SDA data is stored directly into the serial register at the rising edge of SLK. As a result, register operation begins immediately after the register LSB has been latched in on the rising edge of SCK.
VD Synchronous Register Operation
There are two types of control registers, VD synchronous and VD asynchronous, as indicated in the Address column of Table I. Register writes to synchronous and asynchronous type registers operate differently as described in the following sections. All writes to system, Mode_A, and Mode_B registers occur asynchronously.
For VD synchronous type registers, SDA data is temporarily stored in a buffer register upon completion of clocking in the last register LSB. This data is held in the temporary buffer register until the next rising edge of VD is applied. Once the next rising edge of VD occurs, the buffered register data is loaded into the serial register, and register operation begins. See Figure 7. Control registers at addresses 0x08, 0x09, 0x10, 0x11, and 0x12 are VD synchronous type registers.
OPERATION OF VD SYNCHRONOUS TYPE REGISTER WRITES BEGIN AT THE NEXT VD RISING EDGE.
VD
HD
VCKM
PROGRAMMING VD SYNCHRONOUS TYPE REGISTERS MUST BE COMPLETED AT LEAST FOUR VCKM CYCLES BEFORE THE RISING EDGE OF VD.
Figure 7. VD Synchronous Type Register Writes
REV. 0
-19-
D2 D1 D0 2
AD9937
SYSTEM OVERVIEW
Figure 8 shows the typical system block diagram for the AD9937. The CCD output is processed by the AD9937's AFE circuitry, which consists of a CDS, VGA, black level clamp, and A/D converter. The digitized pixel information is sent to the digital image processor chip, which performs the postprocessing and compression. To operate the CCD, all CCD timing parameters are programmed into the AD9937 from the system microprocessor, through the 3-wire serial interface. From the system master clock, VCKM provided by the image processor or external crystal, the AD9937 generates all of the CCD's horizontal and vertical clocks and all internal AFE clocks.
CCD VOUT 0.1 F
The H-drivers for H1(A-D) and H2(A,B), and RS are included in the AD9937, allowing these clocks to be directly connected to the CCD. H-drive voltage of up to 3.6 V is supported. An external V-driver is required for the vertical transfer clocks and sensor gate pulses. Figure 9 shows the horizontal and vertical counter dimensions for the AD9937. All internal horizontal and vertical clocking is programmed using these dimensions to specify line and pixel locations.
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTALCOUNTER = 4096 PIXELS MAX
AD9937
CCDIN CIN REGISTER DATA ADCOUT
SERIAL INTERFACE
DIGITAL IMAGE PROCESSING ASIC
V-DRIVE
BUFFER CCD TIMING
TIMING GENERATOR
Figure 8. Typical System Block Diagram, Master Mode
Figure 9. Horizontal and Vertical Counters
MAX VD LENGTH IS 2048 LINES
VD
MAX HD LENGTH IS 4095 PIXELS
HD
VCKM
Figure 10. Maximum VD/HD Dimensions
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11-BIT VERTICAL COUNTER = 2048 LINES MAX
DIGITAL OUTPUTS
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AD9937
ANALOG FRONT END DESCRIPTION AND OPERATION Correlated Double Sampler
The AD9937 AFE signal processing chain is shown in Figure 11. Each processing step is essential in achieving a high quality image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 F series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V to be compatible with the 3 V analog supply of the AD9937.
The CDS circuit samples each CCD pixel twice to extract the video information and reject low frequency noise. The timing diagram in Figure 13 illustrates how the two internally generated CDS clocks, SHP and SHD, are used to sample the reference level and the data level, respectively, of the CCD signal. The placement of the SHP and SHD sampling edges is determined by the setting of the SHPLOC (addr 0x05) and SHDLOC (addr 0x05) control registers. Placement of these two clock edges is critical in achieving the best performance from the CCD.
1.0 F REFB DC RESTORE 1.5V SHP SHD 6dB TO 40dB 0.1 F CCDIN CDS VGA ADC 1.0V
1.0 F REFT 2.0V
AD9937
INTERNAL VREF 2V FULL SCALE OUTPUT DATA LATCH
DOUT PHASE
10 DOUT
10 VGA GAIN REGISTER 8-BIT DAC
OPTICAL BLACK CLAMP CLPOB DIGITAL FILTER 8
SHP
DOUT SHD PHASE
CLPOB CLAMP LEVEL REGISTER
PRECISION TIMING GENERATION
V-H TIMING GENERATION
Figure 11. AFE Block Diagram
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AD9937
PRECISION TIMING HIGH SPEED TIMING GENERATION High Speed Clock Programmability
The AD9937 generates flexible high speed timing signals using the precision timing core. This core is the foundation for generating the timing used for both the CCD and the AFE: the reset gate RS, horizontal drivers H1(A-D) and H2(A, B), and the CDS sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling.
Timing Resolution
Figure 13 shows how the high speed clocks RS, H1-H2, SHP, and SHD are generated. The RS and H1 pulse have positive and negative edge programmability by using control registers (addr 0x06). The H2 clock is always the inverse of H1. Table VIII summarizes the high speed timing registers and the parameters for the high speed clocks. Each register is six bits wide with the 2 MSB used to select the quadrant region as outlined in Table IX. Figure 14 shows the range and default locations of the high speed clock signals.
H-Driver and RS Outputs
The precision timing core uses a 13 master clock input (VCKM) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 12 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. Using a 12 MHz VCKM frequency, the edge resolution of the precision timing core is 1.7 ns. A 24 MHz VCKM frequency can be applied to the AD9937 where the AD9937 will internally divide the VCKM frequency by 2. VCKM frequency division by 2 is controlled by using the VCKM_DIVIDE control (addr 0x04) register.
In addition to the programmable timing positions, the AD9937 features on-chip output drivers for the RS and H1-H2 outputs. These drivers are powerful enough to directly drive the CCD inputs. The H-driver current can be adjusted for optimum rise/ fall time into a particular load by using the H1DRV and H2DRV control registers (addr 0x07). The RS drive current is adjustable using the RSDRV control register (addr 0x07). The H1DRV, H2DRV, and RSDRV registers are adjustable in 1.75 mA increments. All DRV registers have setting of 0 equal to OFF or three-state, and the maximum setting of 7.
POSITION VCKM
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
t VCKMDLY
1 PIXEL PERIOD
PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. THERE IS A FIXED DELAY FROM THE VCKM INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (t VCKMDLY = 6ns TYP).
Figure 12. High Speed Clock Resolution from VCKM Master Clock
3 CCD SIGNAL (INTERNAL) CDS 4
1 RS
2
5 H1
6
H2
PROGRAMMABLE CLOCK INFORMATION 1. RG RISING EDGE (PROGRAMMABLE AT CONTROL REGISTER RSPOSLOC (ADDR 0x06)) 2. RG FALLING EDGE (PROGRAMMABLE AT CONTROL REGISTER RSNEGLOC (ADDR 0x06)) 3. SHP SAMPLE LOCATION (PROGRAMMABLE AT CONTROL REGISTER SHPLOC (ADDR 0x05)) 4. SHD SAMPLE LOCATION (PROGRAMMABLE AT CONTROL REGISTER SHDLOC (ADDR 0x05)) 5. H1 RISING EDGE LOCATION (PROGRAMMABLE AT CONTROL REGISTER H1POSLOC (ADDR 0x06)) 6. H1 NEGATIVE EDGE LOCATION (PROGRAMMABLE AT CONTROL REGISTER H1NEGLOC (ADDR 0x06)) 7. H2 IS ALWAYS THE INVERSE OF H1.
Figure 13. High Speed Clock Programmable Locations
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Table VIII. RS, H1, SHP, SHD, and DOUTPHASE Timing Parameters
Register Name* RSPOSLOC RSNEGLOC H1POSLOC H1NEGLOC SHPLOC SHDLOC DOUTPHASE
Bit Width (Bits) 6 6 6 6 6 6 6
Register Type Control (Addr 0x06) Control (Addr 0x06) Control (Addr 0x06) Control (Addr 0x06) Control (Addr 0x05) Control (Addr 0x05) Control (Addr 0x05)
Range 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location
Description Falling Edge Location for RS Falling Edge Location for RS Positive Edge Location for H1 Negative Edge Location for H1 Sample Location for SHP Sample Location for SHD Phase Location of Data Output [9:0]
*The 2 MSB bits are used to select the quadrant.
Table IX. Precision Timing Edge Locations for RS, H1, SHP, SHD, and DOUTPHASE
Signal Name RS
Quadrant (Range) I II III IV P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47]
RS Rising Edge RSPOSLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 H1 Rising Edge H1POSLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 CDS (SHP) Rising Edge SHPLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 DOUT Rising Edge DOUTPHASE 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011
RS Falling Edge RSNEGLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 H1 Falling Edge H1NEGLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 CDS (SHD) Falling Edge SHDLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 DOUT Falling Edge (Not Programmable) DOUTPHASE + 24 Steps DOUTPHASE + 24 Steps DOUTPHASE + 24 Steps DOUTPHASE + 24 Steps
Signal Name H1
Quadrant (Range) I II III IV P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47]
Signal Name CDS (Internal)
Quadrant (Range) I II III IV P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47]
Signal Name Data Output[9:0]
Quadrant (Range) I II III IV P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47]
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AD9937
POSITION PIXEL PERIOD RSr[0] RS RSf[12] P[0] P[12] P[24] P[36] P[48] = P[0]
Hr[0] H1
Hf[24]
CDS (INTERNAL)
SHP[24] CCD SIGNAL
t S1
SHD[48]
Figure 14. High Speed Clock Default and Programmable Locations
t RISE
H1 H2
t PD < t RISE
H1 FIXED CROSSOVER VOLTAGE
t PD
H2
Figure 15. H-Clock Inverse Phase Relationship
P[0] PIXEL PERIOD P[12] P[24] P[36] P[48] = P[0]
VCLK
t OD
DOUT
1. DOUTPHASE REGISTER (ADDR 0x05) CAN BE USED TO SHIFT THE PHASE OF VCLK AND DOUT TOGETHER WITH RESPECT TO P[0]. 2. DOUT[9:0] CAN BE INDEPENDENTLY DELAYED WITH RESPECT TO VCLK BY USING DOUT_DELAY REGISTER (ADDR 0x05).
Figure 16. Digital Output Phase Adjustment
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MASTER AND SLAVE MODE OPERATION Individual HMASK Sequence
The AD9937 defaults at power up into slave mode operation. During slave mode operation, the VD and HD pins are configured as inputs for external VD and HD signals. The AD9937 can be configured into master mode operation to output the VD and HD signals by programming MASTER = 1 (control addr 0x05).
HORIZONTAL AND VERTICAL TIMING
The HMASK programmable timing shown in Figure 18 provides two HMASK toggle positions and an H1MASK polarity setting. These registers can be used to disable the horizontal H1 and H2 outputs during the vertical transfer period. As shown in Figure 18, the H2(A, B) outputs are always the opposite polarity of the H1(A-D) outputs. The H1MASKSTART and H1MASKSTOP registers reference the 11-bit VD counter.
Individual PBLK Sequences
The internal VD and HD synchronization timing is configured by using the registers in Table X. As shown in Figure 17, the HD and VD clock positions are referenced to the 12-bit H-counter and 11-bit V-counter, respectively. This allows for a maximum of 4096 horizontal pixels by 2048 vertical line resolution. The AD9937 provides programmability for two HD pulses per line with the ability to independently set the last line length by using the HDLASTLEN register (Mode_Reg(4)). Additionally, the HDLENx (where x = 0, 1, 2, 3, 4 representing CCD regions) registers can be used to set different line lengths for each CCD region. As shown in Figure 31, up to five unique CCD regions may be specified.
Up to two individual PBLK pulses can be programmed per line using the registers in Table XI. During the time PBLK is active, the DOUT[9:0] data is fixed at the level set in the PBLK_LEVEL (control addr 0x03) register. Figures 19, 20, and 21 provide examples of PBLK registers described in Table XI.
Table X. HD and VD Registers
Register Name VDLEN VDTOG1 VDTOG2 HDTOG1 HDTOG2 HDTOG3 HDTOG4 HDLASTLEN HDLEN0 HDLEN1 HDLEN2 HDLEN3 HDLEN4 VDHD_INVERT
Length (Bits) 11 4 4 12 12 12 12 12 12 12 12 12 12 1
Register Type Mode_Reg(4) Mode_Reg(4) Mode_Reg(4) Mode_Reg(2) Mode_Reg(2) Mode_Reg(3) Mode_Reg(3) Mode_Reg(4) Mode_Reg(15) Mode_Reg(16) Mode_Reg(17) Mode_Reg(18) Mode_Reg(19) Control 0x04
Range 0-2047 Line Number 0-15 Pixel Location 0-15 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location HIGH/LOW
Description 11-Bit VD Counter Length VD Toggle Position 1. See Figure 17. VD Toggle Position 2. See Figure 17. HD Toggle Position 1. See Figure 17. HD Toggle Position 2. See Figure 17. HD Toggle Position 3. See Figure 17. HD Toggle Position 4. See Figure 17. HD Last Line Length. See Figure 17. 12-Bit HD Counter Length Value for CCD Region 0 12-Bit HD Counter Length Value for CCD Region 1 12-Bit HD Counter Length Value for CCD Region 2 12-Bit HD Counter Length Value for CCD Region 3 12-Bit HD Counter Length Value for CCD Region 4 VD and HD Inversion Control
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AD9937
VDLEN 11-BIT VD COUNTER 000 001 002 003 N-1 N 2048 000 001
12-BIT HD COUNTER HDLENx* HDLASTLEN
VD
1
2
3
HD 4
5
6
7 OPTIONAL SECOND HD PULSE PER LINE
*X = 0, 1, 2, 3, 4 REPRESENTING CCD REGIONS
PROGRAMMABLE CLOCK POSITIONS 1. VDHD_INVERT (PROGRAMMABLE AT CONTROL 0x04) 2. VDTOG1 (PROGRAMMABLE AT MODE_REG(4)) 3. VDTOG2 (PROGRAMMABLE AT MODE_REG(4)) 4. HDTOG1 (PROGRAMMABLE AT MODE_REG(2))
5. HDTOG2 (PROGRAMMABLE AT MODE_REG(2)) 6. HDTOG3 (PROGRAMMABLE AT MODE_REG(3)) 7. HDTOG4 (PROGRAMMABLE AT MODE_REG(3))
Figure 17. VD and HD Programmable Locations
11-BIT VD COUNTER
VD
HMASK
1
2
H1(A-D)
3
H1(A-D)
H1(A, B)
PROGRAMMABLE CLOCK POSITIONS 1. HMASKSTART (PROGRAMMABLE AT MODE_REG(12)) 2. HMASKSTOP (PROGRAMMABLE AT MODE_REG(12)) 3. H1MASKPOL (PROGRAMMABLE AT MODE_REG(12)) THE POLARITY OF H1(A-D) DURING BLANKING IS PROGRAMMABLE (H2(A, B) IS ALWAYS THE OPPOSITE POLARITY OF H1 (A-D))
Figure 18. Programmable Clock Positions for HMASK
Table XI. PBLK Registers
Register Name PBLK_LEVEL PBLKTOG1 PBLKTOG2 PBLKTOG3 PBLKTOG4 PBLKSTART PBLKSTOP
Length (Bits) 1 12 12 12 12 11 11
Register Type Control 0x03 Mode_Reg(9) Mode_Reg(9) Mode_Reg(10) Mode_Reg(10) Mode_Reg(11) Mode_Reg(11)
Range HIGH/LOW 0-4095 Pixel Locations 0-4095 Pixel Locations 0-4095 Pixel Locations 0-4095 Pixel Locations 0-2047 Line Number 0-2047 Line Number -26-
Description 0 = Blank Output Data to Zero, 1 = Blank Output Data to REFBLACK Sets PBLK Toggle Position 1 within the Line Sets PBLK Toggle Position 2 within the Line Sets PBLK Toggle Position 3 within the Line Sets PBLK Toggle Position 4 within the Line Sets the Line Number the PBLK Pulse Will Start In Sets the Line Number the PBLK Pulse Will Stop In REV. 0
AD9937
12-BIT HD COUNTER
PBLK
1
2
3
4
PROGRAMMABLE CLOCK POSITIONS 1. PBLKTOG1 (PROGRAMMABLE AT MODE_REG(9)) 2. PBLKTOG2 (PROGRAMMABLE AT MODE_REG(9)) 3. PBLKTOG3 (PROGRAMMABLE AT MODE_REG(10)) 4. PBLKTOG4 (PROGRAMMABLE AT MODE_REG(10))
Figure 19. PBLK Timing
HDLEN = 1500 PBLKTOG1 = 500 PBLKTOG2 = 785
12-BIT HD COUNTER
PBLK 1. PBLKTOG1 = 500 2. PBLKTOG2 = 785 3. PBLKTOG3 = 4095 4. PBLKTOG4 = 4095 5. THIS PBLK PULSE SEQUENCE IS USED IN THE EXAMPLE BELOW.
11-BIT VD COUNTER
N-4
N-3
N-2
N-1
N
000
001
002
003
VD 500 785 500 785 500 500 785 500 785 500 785
12-BIT HD COUNTER
PBLKSTART
PBLKSTOP
1. PBLKSTART = N - 2 2. PBLKSTOP = 001 3. THIS EXAMPLE SHOWS HOW PBLK IS LOW IN THE VERTICAL BLANKING REGION FROM PBLKTOG1 IN LINE PBLKSTART UNTIL PBLKTOG2 IN LINE PBLKSTOP. AS SHOWN IN THE ABOVE FIGURE, PBLK REMAINS LOW FROM PBLKTOG1 TO PBLKTOG2.
Figure 20. Example of PBLK Applied in Vertical Blanking Region Using PBLKSTART and PBLKSTOP Registers
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AD9937
11-BIT VD COUNTER 000 001 002 003 004 N-1 N
12-BIT HD COUNTER
VD
HD
PBLK
Figure 21. Example with PBLKSTOP = PBLKSTART = 2048
Controlling CLPOB Clamp Pulse Timing
Up to two individual CLPOB pulses can be programmed per line using the CLPOBTOGx (x = 1, 2, 3, 4) registers in Table XII. As shown in Figure 19, these registers reference the 12-bit HD counter. Additional CLPOBENn (n = 0, 1, 2, 3, 4) registers are
provided that allow for independently enabling and disabling the CLPOB pulse in each region of the CCD. Figure 23 shows an example of disabling the CLPOB pulse while operating in CCD region 1.
Table XII. CLPOB Registers
Register Name CLPOBTOG1 CLPOBTOG2 CLPOBTOG3 CLPOBTOG4 CLPOBEN0 CLPOBEN1 CLPOBEN2 CLPOBEN3 CLPOBEN4
Length (Bits) 12 12 12 12 1 1 1 1 1
Register Type Mode_Reg(5) Mode_Reg(5) Mode_Reg(6) Mode_Reg(6) Mode_Reg(15) Mode_Reg(16) Mode_Reg(17) Mode_Reg(18) Mode_Reg(19)
Range 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled
Description First Toggle Position for CLPOB First Toggle Position for CLPOB First Toggle Position for CLPOB First Toggle Position for CLPOB CCD Region 0 CLPOB Enable Disable Control CCD Region 1 CLPOB Enable Disable Control CCD Region 2 CLPOB Enable Disable Control CCD Region 3 CLPOB Enable Disable Control CCD Region 4 CLPOB Enable Disable Control
12-BIT HD COUNTER
HD
CLPOB
1
2
3
4
PROGRAMMABLE CLOCK POSITIONS 1. CLPOBTOG1 (PROGRAMMABLE AT MODE_REG(5)) 2. CLPOBTOG2 (PROGRAMMABLE AT MODE_REG(5)) 3. CLPOBTOG3 (PROGRAMMABLE AT MODE_REG(6)) 4. CLPOBTOG4 (PROGRAMMABLE AT MODE_REG(6))
Figure 22. CLPOB Toggle Positions
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AD9937
CCD REGION 0 VD CCD REGION 1 CCD REGION 2
HD
CLPOB
Figure 23. Example with CLPOBEN1 = 0
Vertical Sensor Transfer Gate Timing
SHUTTER TIMING CONTROL
The vertical transfer sensor gate (TG) pulses are used to transfer the pixel charges from the light-sensitive image area into the light-shielded vertical registers. When a mechanical shutter is not being used, this transfer effectively ends the exposure period during the image acquisition. From the light-shield vertical registers, the image is then read out line by line using the vertical transfer pulses in conjunction with the high speed horizontal clocks. The AD9937 provides four programmable vertical transfer gate pulses (TG1A, TG1B, TG3A, and TG3B). Table XIII lists the TG registers. Two unique TG pulses can be preprogrammed using the TGTOG_x (x = 0, 1) registers. As shown in Figure 24, these toggle registers reference the 12-bit H counter for resolution control at the pixel level. Once the toggle positions have been programmed, the TGPATSELx (x = 0, 1) can be used to select which of the two TG pulses will be output on the TG1A/ B and TG3A/B pins. The TG1A/B and TG3A/B outputs are selected as a group. As a result, the TG1A and TG1B outputs will always be the same. This also applies for the TG3A and TG3B outputs. For example, if TGPATSEL0 = 0, TG1A and TG1B will have the outputs provided by the TGTOG1_0 and TGTOG2_0 registers. The TGMASK register can be used to individually mask (disable) any one of the TG outputs. For example, if TGMASK = 1, the TG1A will not be output. All TG outputs can be disabled by setting TGEN = 0.
CCD image exposure is controlled through use of the substrate clock signal (OFD), which pulses the CCD substrate to clear out accumulated charge. The AD9937 supports two types of OFD shutter timing: normal shutter mode and high precision shutter mode. The registers used for OFD programming are described in Table XIV.
Normal Shutter Mode
Figure 24 shows the VD and OFD output for normal shutter mode. Programming the OFD outputs is similar to programming the TG pulse whereas two unique OFD pulses can be preprogrammed using the OFDTOG_x (x = 0, 1) registers. The OFDTOG_x registers reference the 12-bit HD counter as shown in Figure 24. Once the toggle positions have been programmed, the OFDPATSEL register is used to select which of the two preprogrammed OFD pulses will be output. The OFD will pulse once per line for as many lines set in the OFDNUM register.
High Precision Shutter Mode
High precision shuttering is controlled in the same way as normal shuttering but requires a second set of shutter registers. In this mode, the OFD still pulses once per line, but the last OFD in the field will have an additional OFD pulse whose location is determined by the OFDHPTOG1 and OFDHPTOG2 registers. An example of this is shown in Figure 25. Finer resolution of the exposure time is possible using this mode. Leaving both OFDHPTOG registers set to 4095 disables the high precision shutter mode (default setting).
Table XIII. TG Registers
Register Name TGEN TGTOG1_0 TGTOG2_0 TGTOG1_1 TGTOG2_1 TGACTLINE TGPATSEL0 TGPATSEL1 TGMASK
Length (Bits) 1 12 12 12 12 7 1 1 4
Register Type Control 0x10 Shut_Reg(1) Shut_Reg(1) Shut_Reg(2) Shut_Reg(2) Mode_Reg(1) Mode_Reg(1) Mode_Reg(1) Mode_Reg(1)
Range High/Low 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-127 Pixel Location High/Low High/Low 4 Individual Bits
Description TG Output Enable Control (0 = Disable, 1 = Enable) TG0 Pulse Toggle Position 1 TG0 Pulse Toggle Position 2 TG1 Pulse Toggle Position 1 TG1 Pulse Toggle Position 2 Line in Field where TG Outputs are Active TG1 A/B Pattern Selector (0 = TG0, 1 = TG1) TG3 A/B Pattern Selector (0 = TG0, 1 = TG1) TG Masking Control (0 = No Masking, 1 = Mask TG1A, 2 = Mask TG1B, 3 = Mask TG3A, 4 = Mask TG3B)
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Table XIV. OFD Registers
Register Name OFDEN OFDNUM OFDHPTOG1 OFDHPTOG2 OFDTOG1_0 OFDTOG2_0 OFDTOG1_1 OFDTOG2_1 OFDPATSEL
Length (Bits) 1 11 12 12 12 12 12 12 1
Register Type Control 0x10 Control 0x10 Control 0x11 Control 0x11 Shut_Reg(3) Shut_Reg(3) Shut_Reg(4) Shut_Reg(4) Mode_Reg(1)
Range High/Low 0-2048 Pulses 0-4095 Pixel Locations 0-4095 Pixel Locations 0-4095 Pixel Locations 0-4095 Pixel Locations 0-4095 Pixel Locations 0-4095 Pixel Locations High/Low
Description OFD Output Enable Control (0 = Disable, 1 = Enable) Total Number of OFD Pulses per Field High Precision Toggle Position 1. See Figure 24. High Precision Toggle Position 2. See Figure 24. OFD0 Pulse Toggle Position 1 OFD0 Pulse Toggle Position 2 OFD1 Pulse Toggle Position 1 OFD1 Pulse Toggle Position 2 OFD Pattern Selector (0 = OFD0, 1 = OFD1)
11-BIT VD COUNTER
000
001
002
003
N-1
N
2048
000
001
12-BIT HD COUNTER LAST LINE VD
1 HD
TG1A TG1B
2
3
TG3A TG3B
4
5
t EXP
OFD 6 7
PROGRAMMABLE CLOCK POSITIONS 1. TGACTLINE (PROGRAMMABLE AT MODE_REG(1)) 5. TGTOG2_1 (PROGRAMMABLE AT SHUT_REG(2)) 2. TGTOG1_0 (PROGRAMMABLE AT SHUT_REG(1)) 6. OFDTOG1_0 (PROGRAMMABLE AT SHUT_REG(3)) 3. TGTOG2_0 (PROGRAMMABLE AT SHUT_REG(1)) 7. OFDTOG2_0 (PROGRAMMABLE AT SHUT_REG(3)) 4. TGTOG1_1 (PROGRAMMABLE AT SHUT_REG(2))
Figure 24. Horizontal Timing Example with TGACTLINE = 1 and OFDNUM = 2
VD
HD LAST LINE TG1A TG1B
TG3A TG3B
t EXP
OFD PROGRAMMABLE CLOCK POSITIONS 1. OFDHPTOG1 (PROGRAMMABLE AT CONTROL REGISTER 0x11) 2. OFDHPTOG2 (PROGRAMMABLE AT CONTROL REGISTER 0x11) 1 2 SECOND OFD PULSE ADDED IN THE LAST LINE FOR GREATER EXPOSURE CONTROL PRECISION
Figure 25. High Precision
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Controlling LM Pulse Timing
The AD9937 provides an LM output pulse that is fully programmable by using the registers in Table XV. Two unique sets of LM pulses can be preprogrammed using the LMLENx, LMTOG1_x, and LMTOG2_x (x = 0, 1) registers. Once these pulses are preprogrammed, they can be individually selected to be output in any of the five CCD regions by using the LMPATSELn register (n = 0, 1, 2, 3, 4). The number of repetitions can also be individually programmed for each CCD region by using the LMREPn register (n = 0, 1, 2, 3, 4). The 12-bit H counter and 8-bit LM counters are used for configuring the LM pulse. The 8-bit LM counter resets to 0 when
the 12-bit H counter resets to 0 set by the HDLEN register. The LMSTART0 and LMSTART1 positions reference the 12bit H counter value zero. The 8-bit LM counter begins counting when LMSTART0 is reached; it counts up to the value set in the LMLENx register, as shown in Figure 26. The LM pulse toggle positions reference the 8-bit LM counter. Figures 26 and 27 provide examples of programming the LM pulses. Figure 26 shows an example when LMSTART1 is less than HDLEN. In this case, multiple sets of LM pulses can be output between the HDLEN lengths. The number of sets is determined by the value of HDLEN and LMSTART1. Figure 27 shows that only one set of LM pulses will be output when LMSTART1 is greater than HDLEN.
Table XV. LM Registers
Register Name LM_INVERT LMSTART0* LMSTART1* LMLEN0 LMTOG1_0 LMTOG2_0 LMLEN1 LMTOG1_1 LMTOG2_1 LMPATSEL0 LMREP0 LMPATSEL1 LMREP1 LMPATSEL2 LMREP2 LMPATSEL3 LMREP3 LMPATSEL4 LMREP4
Length (Bits) 1 12 12 8 8 8 8 8 8 1 2 1 2 1 2 1 2 1 2
Register Type Control 0x04 Mode_Reg(13) Mode_Reg(13) HLM_Reg(8) HLM_Reg(8) HLM_Reg(8) HLM_Reg(9) HLM_Reg(9) HLM_Reg(9) Mode_Reg(15) Mode_Reg(15) Mode_Reg(16) Mode_Reg(16) Mode_Reg(17) Mode_Reg(17) Mode_Reg(18) Mode_Reg(18) Mode_Reg(19) Mode_Reg(19)
Range High/Low 0-4095 Pixels 0-4095 Pixels 0-255 Pixels 0-255 Pixels 0-255 Pixels 0-255 Pixels 0-255 Pixels 0-255 Pixels High/Low 0-3 LM Repetitions High/Low 0-3 LM Repetitions High/Low 0-3 LM Repetitions High/Low 0-3 LM Repetitions High/Low 0-3 LM Repetitions
Description LM Inversion Control (1 = Invert Programmed LM) LM Counter Start Position 1 LM Counter Start Position 2 LM Counter Length for LM0 LM0 Toggle Position 1 LM0 Toggle Position 2 LM Counter Length for LM1 LM1 Toggle Position 1 LM1 Toggle Position 2 Selects CCD Region 0 LM Pattern (0 = LM0, 1 = LM1) LM Repetition Number in CCD Region 0 Selects CCD Region 1 LM Pattern (0 = LM0, 1 = LM1) LM Repetition Number in CCD Region 1 Selects CCD Region 2 LM Pattern (0 = LM0, 1 = LM1) LM Repetition Number in CCD Region 2 Selects CCD Region 3 LM Pattern (0 = LM0, 1 = LM1) LM Repetition Number in CCD Region 3 Selects CCD Region 4 LM Pattern (0 = LM0, 1 = LM1) LM Repetition Number in CCD Region 4
*LMSTART0 and LMSTART1 reference the 12-bit HD counter.
REV. 0
-31-
AD9937
12-BIT HD COUNTER LMLENx1 8-BIT LM COUNTER LMREPn2 = 3 LMx1 1 2 3
LM PULSE SET 1 LMSTART0 LMSTART1 NOTES
1x = 0, 1 (TWO UNIQUE SETS OF LM OUTPUTS CAN BE PROGRAMMED) 2n = 0, 1, 2, 3, 4 (INDIVIDUAL REPETITION CONTROL FOR EACH CCD REGION)
LM PULSE SET 2
PROGRAMMABLE CLOCK POSITIONS 1. LM_INVERT (PROGRAMMABLE AT CONTROL 0x04) 2. LMTOG1_x (PROGRAMMABLE AT HLM_REG(8)) 3. LMTOG2_x (PROGRAMMABLE AT HLM_REG(8))
Figure 26. Example of LM Pulse with LMSTART1 < HDLEN
12-BIT HD COUNTER LMLENx 8-BIT LM COUNTER LMREPn = 3 LMx
LM PULSE SET 1 LMSTART0
Figure 27. Example of LM Pulse with LMSTART1 > HDLEN
SPECIAL HORIZONTAL PATTERN TIMING
The AD9937 provides the ability to interrupt the normal horizontal H1(A-D) and H2(A, B) clocking in order to apply a special pattern on these outputs. This special horizontal pattern timing occurs during the period when the LM outputs are active. Table XVI lists the registers used to program the special H patterns. Figure 28 provides an example of a special H pattern being applied to the H1A output. The timing diagram shown in Figure 28 identifies the registers associated with outputting the special H patterns. Although only
the H1A output is shown, the same special H timing can be independently configured on the remaining horizontal outputs by using the registers described in Table XVI. As shown in Figure 28, the special H1A output begins when SPHSTARTx is reached. It is important to note that there are two SPHSTART registers. If SPHPATSEL = 0, the SPHSTART0 register will be used, whereas if SPHPATSEL = 1, the SPHSTART1 register will be used. The special H patterns can be enabled and disabled for each of the five CCD regions by using the SPHENx (x = 0, 1, 2, 3, 4).
-32-
REV. 0
AD9937
MASKING H1 AND H2 OUTPUTS
The H1 and H2 outputs can be masked during the horizontal and vertical transfers as shown in Figures 29 and 30.
Horizontal Masking
The H1 clocks are masked with the polarity set by the H1MASKPOL register as shown in Figure 29. The H2 outputs will always be the opposite polarity of H1. The H1 and H2 outputs are masked from HDLEN + 1 to HBLKTOG1 position when HDLASTLEN is the same as HDLEN. In the case when HDLASTLEN is greater than HDLEN, the H1 and H2 outputs
will be masked during the entire last line. It is recommended to always program HBLKTOG3 and HBLKTOG4 to 4095 when only one H-blanking in a line is required. It is also recommended to program HBLKTOG1 < HBLKTOG2 < HBLKTOG3 < HBLKTOG4.
Vertical Masking
As shown in Figure 30, the H1 and H2 outputs remain masked if the horizontal HMASK is followed by the vertical HMASK region or if the vertical HMASK region is followed by the horizontal HMASK region.
Table XVI. Special H Pattern Registers
Register Name HBLKTOG1 HBLKTOG21 HBLKTOG31 HBLKTOG41 H1APOL H1BPOL H1CPOL H1DPOL H2APOL H2BPOL SPHSTART02 SPHSTART12 SPH1A1 SPH1B1 SPH1C1 SPH1D1 SPH2A1 SPH2B1 SPH1A2 SPH1B2 SPH1C2 SPH1D2 SPH2A2 SPH2B2 SPH1A3 SPH1B3 SPH1C3 SPH1D3 SPH2A3 SPH2B3 SPHEN0 SPHEN1 SPHEN2 SPHEN3 SPHEN4
1
Length (Bits) 12 12 12 12 1 1 1 1 1 1 8 8 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 1 1 1 1
Register Type Mode_Reg(7) Mode_Reg(7) Mode_Reg(8) Mode_Reg(8) HLM_Reg(1) HLM_Reg(1) HLM_Reg(1) HLM_Reg(1) HLM_Reg(1) HLM_Reg(1) HLM_Reg(8) HLM_Reg(9) HLM_Reg(2) HLM_Reg(2) HLM_Reg(2) HLM_Reg(3) HLM_Reg(3) HLM_Reg(3) HLM_Reg(4) HLM_Reg(4) HLM_Reg(4) HLM_Reg(5) HLM_Reg(5) HLM_Reg(5) HLM_Reg(6) HLM_Reg(6) HLM_Reg(6) HLM_Reg(7) HLM_Reg(7) HLM_Reg(7) Mode_Reg(15) Mode_Reg(16) Mode_Reg(17) Mode_Reg(18) Mode_Reg(19)
Range 0-4095 Pixel Locations 0-4095 Pixel Locations 0-4095 Pixel Locations 0-4095 Pixel Locations High/Low High/Low High/Low High/Low High/Low High/Low 0-255 Pixel Locations 0-255 Pixel Locations 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits 6 Individual Bits High/Low High/Low High/Low High/Low High/Low
Description HBLK Toggle Position 1 HBLK Toggle Position 2 HBLK Toggle Position 3 HBLK Toggle Position 4 H1A Special H Pattern Start Polarity H1B Special H Pattern Start Polarity H1C Special H Pattern Start Polarity H1D Special H Pattern Start Polarity H2A Special H Pattern Start Polarity H2B Special H Pattern Start Polarity LM Pattern #0 (LM0) Special H Pulse Start Position LM Pattern #1 (LM1) Special H Pulse Start Position H1A Special H Pattern during LM Repetition 1 H1B Special H Pattern during LM Repetition 1 H1C Special H Pattern during LM Repetition 1 H1D Special H Pattern during LM Repetition 1 H2A Special H Pattern during LM Repetition 1 H2B Special H Pattern during LM Repetition 1 H1A Special H Pattern during LM Repetition 2 H1B Special H Pattern during LM Repetition 2 H1C Special H Pattern during LM Repetition 2 H1D Special H Pattern during LM Repetition 2 H2A Special H Pattern during LM Repetition 2 H2B Special H Pattern during LM Repetition 2 H1A Special H Pattern during LM Repetition 3 H1B Special H Pattern during LM Repetition 3 H1C Special H Pattern during LM Repetition 3 H1D Special H Pattern during LM Repetition 3 H2A Special H Pattern during LM Repetition 3 H2B Special H Pattern during LM Repetition 3 Special H Pattern Enable in CCD Region 0 Special H Pattern Enable in CCD Region 1 Special H Pattern Enable in CCD Region 2 Special H Pattern Enable in CCD Region 3 Special H Pattern Enable in CCD Region 4
NOTES 1 The HBLKTOGx toggle positions reference the 12-bit HD counter. 2 The SPHSTART0 and SPHSTART1 toggle positions reference the 8-bit LM counter.
REV. 0
-33-
AD9937
12-BIT HD COUNTER
LMSTART0
8-BIT LM COUNTER
HBLKTOG1
SPHSTARTx
H1A
2
3
4 HBLKTOG2 HBLKTOG3 LMSTART1 HBLKTOG3
5
6
PROGRAMMING NOTES 1. THERE ARE TWO SPHSTART REGISTERS. THEY ARE SPHSTART0 AND SPHSTART1. SPHSTART0 IS USED WHEN THE LM0 PULSE IS SELECTED BY SETTING LMPATSEL = 0. SPHSTART1 IS USED WHEN THE LM1 PULSE IS SELECTED BY SETTING LMPATSEL = 1. 2. THIS REGION REPRESENTS NORMAL H1A OUTPUTS. 3. THIS REGION REPRESENTS SPECIAL H1A PATTERN BEING OUTPUT DURING THE LM REP 1. THE SPH1A1 REGISTER IS USED TO SET THE SPECIAL H1A PATTERN IN THIS REGION. 4. THIS REGION REPRESENTS SPECIAL H1A PATTERN BEING OUTPUT DURING THE LM REP 2. THE SPH1A2 REGISTER IS USED TO SET THE SPECIAL H1A PATTERN IN THIS REGION. 5. THIS REGION REPRESENTS SPECIAL H1A PATTERN BEING OUTPUT DURING THE LM REP 3. THE SPH1A3 REGISTER IS USED TO SET THE SPECIAL H1A PATTERN IN THIS REGION. 6. THIS REGION REPRESENTS NORMAL H1A OUTPUTS.
8-BIT LM COUNTER SPHSTARTx PIXEL CLOCK SPH1A1 SPECIAL H1A 1 1 0 1 0 1
PROGRAMMING NOTES 1. THIS EXAMPLE SHOWS H1A OUTPUT FOR REGION 3 ABOVE. IN THIS EXAMPLE: SPH1A1 = 110101. 2. THE SPECIAL H PATTERN STARTING POLARITY CAN BE INDEPENDENTLY SET FOR EACH H OUTPUT USING THE POL REGISTERS LISTED IN TABLE XVI. NOTE: THE SPECIAL H STARTING POLARITY WILL OCCUR AT THE START OF SPHSTARTx. (ABOVE: H1APOL = 0)
Figure 28. Example of Programming the Special H-Output Patterns
HBLK 131 132 133 134 135 823 824 825
HBLK 868 1559
HMASK
HBLK 1 2 3 4
0 1560
H1TOG34POL H1
H1MASKPOL
H1TOG12POL
H2 HBLKTOG2 HBLKTOG3 HBLKTOG4 HBLKTOG1
Figure 29. Example of Horizontal HMASK Masking
-34-
REV. 0
AD9937
HBLK 131 132 133 134 135 154 155 156 HMASK 233 0 234 1 2 VERTICAL HMASK 1559
HMASK
HBLK 1 2 3 4
0 1560
H1TOG34POL H1
H1MASKPOL
H1TOG12POL
H2 HBLKTOG2 HDLEN HDLASTLEN HBLKTOG1
Figure 30. Example of Vertical HMASK Masking with HDLASTLEN > HDLEN with HMASTKSTART = 0 and HMASKSTOP = 1560
VERTICAL TIMING GENERATION
CCD REGIONS
The AD9937 provides a very flexible solution for generating vertical CCD timing, and can support multiple CCDs and different system architectures. The 4-phase vertical transfer clocks V1-V4 are used to shift each line of pixels into the horizontal output register of the CCD. The AD9937 allows these outputs to be individually programmed into different pulse patterns. Vertical sequence control registers then organize the individual vertical pulses into the desired CCD vertical timing arrangement. The AD9937 can preprogram three unique sets of vertical transfer pulses known as VTP0, VTP1, and VTP2. Each VTP set consists of the four vertical clocks (V1A/B, V2, V3A/B, and V4), as shown in Figure 32. Once preprogrammed, any one of the three unique VTP sets can then be selected to be output in any one of the five CCD regions by using the VTPPATSELx (x = 0, 1, 2, 3, 4) registers. The VTP_Reg(1-9) registers listed in Table II are used for generating the VTP pulse sets. Figure 32 shows an example of programming one VTPx (x = 0, 1, 2) pulse set. Once a VTP pulse set has been configured, multiple repetitions of this set can be repeated to create an entire VTP sequence. This is accomplished by using the VTPREPn (n = 0, 1, 2, 3, 4) registers where n represents the five CCD regions. An example of repeating a VTP set is shown in Figure 33.
Up to five unique CCD regions can be preprogrammed using the sequence change position registers as described in Table XVII. The SCPx (x = 0, 1, 2, 3, 4) registers determine when the settings in Mode_Reg(15-19) are active. For example, the SCP1 register activates the registers at Mode_Reg(16) for CCD region 1. Note that SCP0 is not programmable. The SCP0 position always starts at Line 0, as shown in Figure 31.
CCD REGION 0 REGISTERS LOCATED AT MODE_REG(15) ARE ACTIVE WHILE OPERATING IN CCD REGION 0 SCP1 [7:0] CCD REGION 1 REGISTERS LOCATED AT MODE_REG(16) ARE ACTIVE WHILE OPERATING IN CCD REGION 1 SCP2 [7:0] CCD REGION 2 REGISTERS LOCATED AT MODE_REG(17) ARE ACTIVE WHILE OPERATING IN CCD REGION 2 SCP3 [7:0] CCD REGION 3 REGISTERS LOCATED AT MODE_REG(18) ARE ACTIVE WHILE OPERATING IN CCD REGION 3 SCP4 [7:0] CCD REGION 4 REGISTERS LOCATED AT MODE_REG(19) ARE ACTIVE WHILE OPERATING IN CCD REGION 4 SCP0 (FIXED AT LINE 0)
Figure 31. Sequence Change Positions
Table XVII. Sequence Change Positions Registers
Register Name* SCP1 SCP2 SCP3 SCP4
Length (Bits) 8 8 8 8
Register Type Mode_Reg(14) Mode_Reg(14) Mode_Reg(14) Mode_Reg(14)
Range 0-255 Line Positions 0-255 Line Positions 0-255 Line Positions 0-255 Line Positions
Description Sequence Change Position 1 Sequence Change Position 2 Sequence Change Position 3 Sequence Change Position 4
*There is no SCP0 register. The SCP0 position is always fixed at Line 0.
REV. 0
-35-
AD9937
12-BIT HD COUNTER
V1A/B
1
5
6
2 V2 7 8
3 V3A/B 9 10
V4
4
11
12
VTPLEN_x* PROGRAMMING NOTES *(x = 0, 1, 2) THE x REPRESENTS THE THREE SEPARATE REGISTERS FOR VTP0, VTP1, AND VTP2 SETS. THIS ALSO APPLIES TO THE x USED IN THE PROGRAMMABLE CLOCK POSITIONS BELOW. PROGRAMMABLE CLOCK POSITIONS 1. V1POL_x (PROGRAMMABLE AT VTP_REG(x)) 2. V2POL_x (PROGRAMMABLE AT VTP_REG(x)) 3. V3POL_x (PROGRAMMABLE AT VTP_REG(x)) 4. V4POL_x (PROGRAMMABLE AT VTP_REG(x)) 5. V1TOG1_x (PROGRAMMABLE AT VTP_REG(x)) 6. V1TOG2_x (PROGRAMMABLE AT VTP_REG(x))
7. V2TOG1_x (PROGRAMMABLE AT VTP_REG(x)) 8. V2TOG2_x (PROGRAMMABLE AT VTP_REG(x)) 9. V3TOG1_x (PROGRAMMABLE AT VTP_REG(x)) 10. V3TOG2_x (PROGRAMMABLE AT VTP_REG(x)) 11. V4TOG1_x (PROGRAMMABLE AT VTP_REG(x)) 12. V4TOG2_x (PROGRAMMABLE AT VTP_REG(x))
Figure 32. Example of Programming One VTP Pulse
VTPREPn* = 2 12-BIT HD COUNTER
V1A/B
75
250
355
530
V2
40
145
320
425
V3A/B
110
215
390
495
V4
5
180
285
460
VTPLEN_x *(n = 0, 1, 2, 3, 4) n REPRESENTS THE NUMBER OF PROGRAMMABLE CCD REGIONS. THE NUMBER OF REPETITIONS IN EACH CCD REGION CAN BE INDEPENDENTLY SET USING THE VTPREP REGISTER FOR THAT REGION.
Figure 33. Example of Creating a Sequence of VTP Pulses by Using the VTPREP Register
-36-
REV. 0
AD9937
12-BIT HD COUNTER VTPLEN_0 V1A/B VTPLEN_1 VTPLEN_2
V2
V3A/B
V4
VTP0
VTP1
VTP2
Figure 34. Example of Three Preprogrammed VTP Pulses
SCP0 (FIXED AT LINE 0) 11-BIT VD COUNTER 000 001
SCP1 = 1
002
N
12-BIT HD COUNTER
VD
HD
V1A/B
V2
V3A/B
V4 VTPPATSEL0 = 1 VREP0 = 1 VTPPATSEL1 = 0 VREP1 = 1
Figure 35. Example of Applying VTP Pulse Sequences to CCD Regions
REV. 0
-37-
AD9937
SCP0 (FIXED AT LINE 0) 11-BIT VD COUNTER 000 001 SCP1 = 1 002 N
12-BIT HD COUNTER
VD
HD
V1A/B
V2
V3A/B
V4 VTPPATSEL0 = 1 VREP0 = 1 VTPPATSEL1 = 0 VREP1 = 2
Figure 36. Example of VTP Pulse Sequence with VREP = 2 in CCD Region 1
-38-
REV. 0
AD9937
VDD (INPUT) 1 INTERNAL POWER-ON AUTO-RESET (LO-ACTIVE)
t PWR1
2
VCKM
4
5
6
7
SERIAL WRITES
OUTCONT (REGISTER CONTROLLED)
1V
VD (OUTPUT)
ODD FIELD
EVEN FIELD
ODD FIELD
1H
HD (OUTPUT)
V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B, OFD, H1(A, B, C, D)
DIGITAL OUTPUTS
RS, H2(A, B), LM
t SETTINGS2
VCLK
t DELAY3
NOTES 1THE INTERNAL POWER-ON AUTO RESET TIME t PWR = 1.0ms REGARDLESS OF THE VCLK CLOCK FREQUENCY.
2IT 3IT
TAKES 500 s FOR VCLK TO SETTLE ONCE THE DIG_STBY REGISTER HAS BEEN PROGRAMMED. TAKES FOUR VCKM CLOCK CYCLES FROM WHEN OUTCONT IS ASSERTED HIGH UNTIL THE VD, HD, AND DIGITAL OUTPUT DATA IS VALID.
Figure 37. Recommended Power-Up Sequence
POWER-UP FOR MASTER MODE Table XVIII. Start-Up Polarities (While OUTCONT = LO)
When the AD9937 is powered up, the following sequence is recommended. (Refer to Figure 37 for each step.) 1. Turn on power supplies for AD9937. 2. The internal power-on auto-reset circuit will deassert 1.0 ms after VDD settles. (All internal registers are reset to the default values.) 3. The VCKM clock can be applied as soon as VDD settles. 4. Reset the internal AD9937 registers: write a 0x000000 to the SW_RESET register (addr 0x00). This will set all internal register values to their default values. (This step is optional because the internal power-on reset circuit is applied at power-up.) 5. Write a 1 to the DIG_STBY and AFE_STBY registers (addr 0x02). This will put the digital and analog circuits into the normal operating mode. 6. Program all control, system, and mode registers. 7. Write a 1 to the OUTCONT_REG (addr 0x01). This will put the digital outputs into the normal operating mode. The internal OUTCONT will be asserted high on the rising edge of the 32nd SCK clock when writing to the OUTCONT_REG. REV. 0 -39-
Output V1A/B V2 V3A/B V4 TG1A TG1B TG3A TG3B OFD H1(A-D) H2(A, B) LM RS
OUTCONT = LO HI HI HI HI HI HI HI HI HI HI LO LO LO
AD9937
VDD (INPUT)
3
VCKM
1
2
5
6
7
SERIAL WRITES
OUTCONT (INTERNAL SIGNAL)
VD (OUTPUT)
HD (OUTPUT) V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B, OFD, H1(A, B, C, D) DIGITAL OUTPUTS RS, H2(A, B), LM
tDELAY*
AFE_STBY (REGISTER)
DIG_STBY (REGISTER)
*IT TAKES 4 VCKM CLOCK CYCLES FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD AND DIGITAL OUTPUT DATA IS VALID.
Figure 38. Recommended Standby Sequence
STANDBY SEQUENCE
The following sequence is recommended when the AD9937 is put into standby operation. (Refer to Figure 38 for each step.) 1. Write a 0 to the OUTCONT_REG register (addr 0x01). 2. Write a 0 to the DIG_STBY and AFE_STBY registers (addr 0x02). This will put the digital and analog circuits into the standby operating mode.
3. Stop VCKM clock. (This is optional.) 4. Apply VCKM when ready to come out of standby operation. 5. Write a 1 to the DIG_STBY and AFE_STBY registers (addr 0x02). This will put the digital and analog circuits into the normal operating mode. 6. Program any necessary control, system, or mode registers. 7. Write a 1 to the OUTCONT_REG register (addr 0x01) to begin operation.
-40-
REV. 0
AD9937
POWER-DOWN SEQUENCE
The following sequence is recommended when AD9937 is being powered down. (Refer to Figure 39 for each step.) 1. Write a 0 to the OUTCONT_REG register (addr 0x01).
2. Write a 0 to the DIG_STBY and AFE_STBY registers (addr 0x02). This will put the digital and analog circuits into the standby operating mode. 3. Stop VCKM clock. 4. Turn off power supplies to AD9937.
4
VDD (INPUT)
3 VCKM
SERIAL WRITES
OUTCONT (INTERNAL)
VD (OUTPUT)
ODD FIELD
EVEN FIELD
ODD FIELD
HD (OUTPUT) V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B, OFD, H1(A, B, C, D) DIGITAL OUTPUTS RS, H2(A, B), LM
VCLK
AFE_STBY (REGISTER)
DIG_STBY (REGISTER)
Figure 39. Recommended Power-Down Sequence
CCD SIGNAL t ID
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
t ID t S2
SHP
t S1
SHD
t CP
CYCLE 2 CYCLE 3 CYCLE 4 CYCLE 5 CYCLE 6 CYCLE 7 CYCLE 8 CYCLE 9
CYCLE 1 VCKM
t OD
OUTPUT DATA N - 10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N
NOTES 1. RECOMMENDED PLACEMENT FOR VCKM RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. 3. OUTPUT DATA LATENCY IS NINE VCKM CYCLES.
Figure 40. Pipeline Latency
REV. 0
-41-
AD9937
CIRCUIT LAYOUT INFORMATION
The AD9937 typical circuit connection is shown in Figure 41. The PCB layout is critical in achieving good image quality from the AD9937 product. All of the supply pins, particularly the AVDD, DVDD, TCVDD, RSVDD, HVDD1, and HVDD2 supplies, must be decoupled to ground with good quality high frequency chip capacitors. The decoupling capacitors should be located as close as possible to the supply pins, and should have a very low impedance path to a continuous ground plane. There should also be a 4.7 F or larger value bypass capacitor for each main supply although this is not necessary for each individual pin. In most applications, it is easier and recommended to share the same supply for AVDD, DVDD, TCVDD, RSVDD, HVDD1, and HVDD2, which may be done as long as the individual supply pins are separately bypassed at each supply pin. A separate 3 V supply should be used for DRVDD with this supply pin decoupled to the same ground plane as the rest of the chip. A separate ground for DRVSS is not recommended.
0.1 F
The analog bypass pins (REFB, REFT) should also be carefully decoupled to ground as close as possible to their respective pins. The analog input (CCDIN) capacitor should also be located close to the pin. The H1(A-D), H2(A, B), and RS printed circuit board traces should be designed to have low inductance to avoid excessive distortion of the signals. Heavier traces are recommended, because of the large transient current demand on H1(A-D) and H2(A, B) by the CCD. If possible, physically locate the AD9937 closer to the CCD to reduce the inductance on these lines. As always, the routing path should be as direct as possible from the AD9937 to the CCD. Careful trace impedance considerations must also be made with applications using a flex printed circuit (FPC) connecting the CCD to the AD9937. FPC trace impedances can be controlled by applying a solid uniform ground plane under the H1(A-D), H2(A, B), and RS traces. This helps minimize the amount of overshoot and ringing on these signals at the CCD inputs.
3V ANALOG SUPPLY
2
VD, HD SERIAL INTERFACE
3
8
OFD, LM, V4, TG3B, V3A/B, TG3A, V2, TG1B, V1A/B, TG1A, TO V-DRIVER
DVDD LM V4
DVSS
TG3B
V3A/B
SCK
SDA SLD
VD HD OFD
TG3A
56 55 54 53 52 51 50 49 48 47 46 45 44 43
V2
NC NC D0 D1 D2 D3
1 2 3 4 5 6 7 8 9 10 11 12
42
TG1B V1A/B TG1A REFB 1.0 F REFT 1.0 F AVSS
PIN 1 IDENTIFIER
41 40 39
AD9937
TOP VIEW (Not to Scale)
38 37
3V DRIVER SUPPLY
DRVSS
4.7 F
0.1 F
DRVDD D4
D5 D6 D7
CCDIN AVDD 35 VCKM 34 TCVDD
36 33 32 31 30 29
0.1 F CCD SIGNAL 3V ANALOG SUPPLY REF CLOCK INPUT 0.1 F
D8 13 D9
14
TCVSS 0.1 F NC NC NC
3V ANALOG SUPPLY 4.7 F
VCLK
H1B HVDD1
HVSS1 H1C H2A
H2B
H1D
H1A
RS RSVDD
HVDD2 HVSS2
RSVSS
DATA OUTPUTS
10
15 16 17 18 19 20 21 22 23 24 25 26 27 28
RS DATA OUTPUT CLOCK 0.1 F 0.1 F 0.1 F 6 H1D, H2B, H1B, H1C, H2A, H1A
3V ANALOG SUPPLY
Figure 41. Typical Circuit Configuration
-42-
REV. 0
AD9937
Figures 42 and 43 show the recommended AD9937 supply grouping. Figure 42 shows how the supplies should be tied together when there are only two available supply sources, whereas Figure 43 shows how the supplies can be tied together when there are three available supply sources. In either case, all grounds should be tied together as shown. Also as shown in Figures 42 and 43 is that the AD9937 DRVDD supply can be shared with the system ASIC/DSP.
AD9937
3V ANALOG SUPPLY AVDD TCVDD HVDD1 HVDD2 RSVDD DVDD DRVDD AVSS TCVSS HVSS1 HVSS2 RSVSS DVSS DRVSS
3V DRIVER SUPPLY
ASIC/DSP
Figure 42. Recommended Supply Grouping with Two Available Supply Sources
3V ANALOG SUPPLY 1
AD9937
AVDD TCVDD DVDD HVDD1 HVDD2 RSVDD DRVDD AVSS TCVSS DVSS HVSS1 HVSS2 RSVSS DRVSS
3V ANALOG SUPPLY 2
3V DRIVER SUPPLY
ASIC/DSP
Figure 43. Recommended Supply Grouping with Three Available Supply Sources
REV. 0
-43-
AD9937
OUTLINE DIMENSIONS 56-Lead Lead Frame Chip Scale Package [LFCSP] (CP-56)
Dimensions shown in millimeters
0.30 0.23 0.18
56 1
8.00 BSC SQ
0.60 MAX 0.60 MAX
43 42
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
7.75 BSC SQ
BOTTOM VIEW
6.25 6.10 SQ 5.95
0.50 0.40 0.30
29 28
15 14
0.25 MIN 1.00 0.85 0.80 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 6.50 REF
12 MAX
0.50 BSC SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
-44-
REV. 0
C03556-0-5/03(0)

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